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Sun, 20 Oct 2019 22:38:51 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id E8DCAF802FB; Sun, 20 Oct 2019 22:38:48 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 18F3DF800C0 for ; Sun, 20 Oct 2019 22:38:44 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 18F3DF800C0 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2019 13:38:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,320,1566889200"; d="scan'208";a="227112525" Received: from crojewsk-mobl1.ger.corp.intel.com (HELO [10.252.18.15]) ([10.252.18.15]) by fmsmga002.fm.intel.com with ESMTP; 20 Oct 2019 13:38:35 -0700 To: Curtis Malainey References: <20191018200449.141123-1-cujomalainey@chromium.org> <20191018200449.141123-12-cujomalainey@chromium.org> From: Cezary Rojewski Message-ID: <6be89c8d-e3d4-311f-667c-8e7096f76fab@intel.com> Date: Sun, 20 Oct 2019 22:38:33 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191018200449.141123-12-cujomalainey@chromium.org> Content-Language: en-US Cc: Oder Chiou , Pierre-Louis Bossart , alsa-devel@alsa-project.org, Kuninori Morimoto , Ben Zhang , Takashi Iwai , Jie Yang , Liam Girdwood , Richard Fontana , Mark Brown , Bard Liao , Thomas Gleixner Subject: Re: [alsa-devel] [PATCH v2 11/12] ASoC: rt5677: Set ADC clock to use PLL and enable ASRC X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On 2019-10-18 22:04, Curtis Malainey wrote: > Use the PLL to kept the correct 24M clock rate so frequency shift does > not occur when using the DSP VAD. > > +static int bdw_rt5677_dsp_hw_params(struct snd_pcm_substream *substream, > + struct snd_pcm_hw_params *params) > +{ > + struct snd_soc_pcm_runtime *rtd = substream->private_data; > + struct snd_soc_dai *codec_dai = rtd->codec_dai; > + int ret; > + > + ret = snd_soc_dai_set_sysclk(codec_dai, RT5677_SCLK_S_PLL1, 24576000, > + SND_SOC_CLOCK_IN); > + if (ret < 0) { > + dev_err(rtd->dev, "can't set codec sysclk configuration\n"); > + return ret; > + } > + ret = snd_soc_dai_set_pll(codec_dai, 0, RT5677_PLL1_S_MCLK, > + 24000000, 24576000); > + if (ret < 0) { > + dev_err(rtd->dev, "can't set codec pll configuration\n"); > + return ret; nitpick: you may skip "return ret" here and drop parenthesis as function's final line does the job. > + } > + > + return ret; If you decide to stick with leaving above as is, explicitly returning 0 would be preferred. > +} _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel