From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9845C43334 for ; Wed, 8 Jun 2022 10:39:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A5E8484328; Wed, 8 Jun 2022 12:39:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=monstr.eu Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=monstr-eu.20210112.gappssmtp.com header.i=@monstr-eu.20210112.gappssmtp.com header.b="IdZssa50"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D878D842EF; Wed, 8 Jun 2022 12:39:19 +0200 (CEST) Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C5DA184307 for ; Wed, 8 Jun 2022 12:39:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=monstr.eu Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=monstr@monstr.eu Received: by mail-ej1-x634.google.com with SMTP id m20so40531018ejj.10 for ; Wed, 08 Jun 2022 03:39:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dm3kDX7DWUNB1AuWO/e3Akm0M+kaBouWjRAHJVeyflg=; b=IdZssa50/lJmkKpm0sRP84Da9aEhkEz1U+0ozTn/Jy0IFDA70qC0JAcnyT23vwjpio IAWWDN4c32os7LXH230wB4XWPl39gkl9Lsk+reKlYjJUtoxWgnMvTFCewiHNxFCv2qki vI3Q4nFFUtFCvfWrdMaglH5G8c+7BcobZvwlrbLp6GSCh4oeUumk6tyDQXhRQSjGVB8e Veq4HzkflFPc4P1qdrxs1p20oU8OlFr36Pz7pHtEbFRYelOMwx8BAKMBlotG77RhHW4j C7LU45YBvNzL+dQ8gPeCnXeQkElqaudH25vPTb8pvBg77ICf6quDB6S4J+8ThaEf6DSf XRBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Dm3kDX7DWUNB1AuWO/e3Akm0M+kaBouWjRAHJVeyflg=; b=d1cFIbBTydZMHNTX4aC1dobUaQEhhZTPfGkMu8txYAdjuqz86LyndV3YwSWexNboa3 WpYYWn4pmYGV4T7v2J/ze7JZ4IqlY7+fylpBaIhrO551Sw+43M+ZdGtn+Yc59J7qDrPG gDOqGS6GZ2ol4qLgruVfU1kI0rfKVQvqPqVxa/v8WnQbqf1oreZD1e44ecpmxuHode58 wMqzN6w28EfJi9y5X8mfcvzZsnvC/pKLNHTg+rzGfNZU6AfkkNI4085LQDfPvPO2mqv7 r8dqcthRDcOVnh+ZBHSD4GFRUkZp3IqdsS10aZssCKr9Z64U4mr6q8qQEbYu8t6IkHa6 euBw== X-Gm-Message-State: AOAM5325fyq4YH0hTdupbJp7jQPLKaR++amxFDJ7tstNP59wfGuOlVXa 78IgYHo5LFFZZMZk30jk132jd/vH/ur8hQ== X-Google-Smtp-Source: ABdhPJyucfAsLkCCjbJfel/NWHH+6qKPhatZ0b9cEpC1Qz5J15coq6eigfWWVp6QKD7DLtYaH/s66Q== X-Received: by 2002:a17:907:60d3:b0:711:cef9:6a85 with SMTP id hv19-20020a17090760d300b00711cef96a85mr14322016ejc.99.1654684746354; Wed, 08 Jun 2022 03:39:06 -0700 (PDT) Received: from localhost ([2a02:768:2307:40d6::f9e]) by smtp.gmail.com with ESMTPSA id u17-20020a056402111100b004316f94ec4esm4194231edv.66.2022.06.08.03.39.05 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Jun 2022 03:39:05 -0700 (PDT) From: Michal Simek X-Google-Original-From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Cc: Bin Meng , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Eugen Hristev , Giulio Benetti , Jim Liu , Michal Simek , Ovidiu Panait , Rick Chen , Sean Anderson , Simon Glass , Stanley Chu Subject: [PATCH 1/2] microblaze: Convert axi timer to DM driver Date: Wed, 8 Jun 2022 12:38:53 +0200 Message-Id: <6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek --- MAINTAINERS | 1 + arch/Kconfig | 5 + arch/microblaze/cpu/Makefile | 2 +- arch/microblaze/cpu/timer.c | 123 ------------------ .../microblaze/include/asm/microblaze_timer.h | 26 ---- drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/xilinx-timer.c | 82 ++++++++++++ 8 files changed, 98 insertions(+), 150 deletions(-) delete mode 100644 arch/microblaze/cpu/timer.c delete mode 100644 arch/microblaze/include/asm/microblaze_timer.h create mode 100644 drivers/timer/xilinx-timer.c diff --git a/MAINTAINERS b/MAINTAINERS index 28e4d3823861..a18762573d93 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -975,6 +975,7 @@ F: drivers/net/xilinx_emaclite.c F: drivers/serial/serial_xuartlite.c F: drivers/spi/xilinx_spi.c F: drivers/sysreset/sysreset_gpio.c +F: drivers/timer/xilinx-timer.c F: drivers/watchdog/xilinx_tb_wdt.c N: xilinx diff --git a/arch/Kconfig b/arch/Kconfig index d91475d24747..3d02d8e71afa 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -75,6 +75,11 @@ config MICROBLAZE bool "MicroBlaze architecture" select SUPPORT_OF_CONTROL imply CMD_IRQ + imply CMD_TIMER + imply SPL_REGMAP if SPL + imply SPL_TIMER if SPL + imply TIMER + imply XILINX_TIMER config MIPS bool "MIPS architecture" diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index ea65a0976eec..1c586a7de023 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,7 +5,7 @@ extra-y = start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o timer.o cpuinfo.o +obj-y += interrupts.o cache.o exception.o cpuinfo.o obj-$(CONFIG_STATIC_RELA) += relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c deleted file mode 100644 index 647bdcd5ba52..000000000000 --- a/arch/microblaze/cpu/timer.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -volatile int timestamp = 0; -microblaze_timer_t *tmr; - -ulong get_timer (ulong base) -{ - if (tmr) - return timestamp - base; - return timestamp++ - base; -} - -void __udelay(unsigned long usec) -{ - u32 i; - - if (tmr) { - i = get_timer(0); - while ((get_timer(0) - i) < (usec / 1000)) - ; - } -} - -#ifndef CONFIG_SPL_BUILD -static void timer_isr(void *arg) -{ - timestamp++; - tmr->control = tmr->control | TIMER_INTERRUPT; -} - -int timer_init (void) -{ - int irq = -1; - u32 preload = 0; - u32 ret = 0; - const void *blob = gd->fdt_blob; - int node = 0; - u32 cell[2]; - - debug("TIMER: Initialization\n"); - - /* Do not init before relocation */ - if (!(gd->flags & GD_FLG_RELOC)) - return 0; - - node = fdt_node_offset_by_compatible(blob, node, - "xlnx,xps-timer-1.00.a"); - if (node != -1) { - fdt_addr_t base = fdtdec_get_addr(blob, node, "reg"); - if (base == FDT_ADDR_T_NONE) - return -1; - - debug("TIMER: Base addr %lx\n", base); - tmr = (microblaze_timer_t *)base; - - ret = fdtdec_get_int_array(blob, node, "interrupts", - cell, ARRAY_SIZE(cell)); - if (ret) - return ret; - - irq = cell[0]; - debug("TIMER: IRQ %x\n", irq); - - preload = fdtdec_get_int(blob, node, "clock-frequency", 0); - preload /= CONFIG_SYS_HZ; - } else { - return node; - } - - if (tmr && preload && irq >= 0) { - tmr->loadreg = preload; - tmr->control = TIMER_INTERRUPT | TIMER_RESET; - tmr->control = TIMER_ENABLE | TIMER_ENABLE_INTR |\ - TIMER_RELOAD | TIMER_DOWN_COUNT; - timestamp = 0; - ret = install_interrupt_handler (irq, timer_isr, (void *)tmr); - if (ret) - tmr = NULL; - } - /* No problem if timer is not found/initialized */ - return 0; -} -#else -int timer_init(void) -{ - return 0; -} -#endif - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On Microblaze it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On Microblaze it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h deleted file mode 100644 index 2ed1651ffcfa..000000000000 --- a/arch/microblaze/include/asm/microblaze_timer.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - */ - -#define TIMER_ENABLE_ALL 0x400 /* ENALL */ -#define TIMER_PWM 0x200 /* PWMA0 */ -#define TIMER_INTERRUPT 0x100 /* T0INT */ -#define TIMER_ENABLE 0x080 /* ENT0 */ -#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ -#define TIMER_RESET 0x020 /* LOAD0 */ -#define TIMER_RELOAD 0x010 /* ARHT0 */ -#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ -#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ -#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ -#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ - -typedef volatile struct microblaze_timer_t { - int control; /* control/statuc register TCSR */ - int loadreg; /* load register TLR */ - int counter; /* timer/counter register */ -} microblaze_timer_t; - -int timer_init(void); diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 7b8ab56ed323..44d1a81bad3d 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -272,4 +272,12 @@ config IMX_GPT_TIMER Select this to enable support for the timer found on NXP i.MX devices. +config XILINX_TIMER + bool "Xilinx timer support" + depends on TIMER + select REGMAP + help + Select this to enable support for the timer found on + any Xilinx boards (axi timer). + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index b2f002d59789..4d06375317e1 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o +obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c new file mode 100644 index 000000000000..75b4473b6397 --- /dev/null +++ b/drivers/timer/xilinx-timer.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 Advanced Micro Devices, Inc + * Michal Simek + * + * (C) Copyright 2007 Michal Simek + * Michal SIMEK + */ + +#include +#include +#include +#include +#include + +#define TIMER_ENABLE_ALL 0x400 /* ENALL */ +#define TIMER_PWM 0x200 /* PWMA0 */ +#define TIMER_INTERRUPT 0x100 /* T0INT */ +#define TIMER_ENABLE 0x080 /* ENT0 */ +#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */ +#define TIMER_RESET 0x020 /* LOAD0 */ +#define TIMER_RELOAD 0x010 /* ARHT0 */ +#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */ +#define TIMER_EXT_COMPARE 0x004 /* GENT0 */ +#define TIMER_DOWN_COUNT 0x002 /* UDT0 */ +#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */ + +#define TIMER_CONTROL_OFFSET 0 +#define TIMER_LOADREG_OFFSET 4 +#define TIMER_COUNTER_OFFSET 8 + +struct xilinx_timer_priv { + struct regmap *regs; +}; + +static u64 xilinx_timer_get_count(struct udevice *dev) +{ + struct xilinx_timer_priv *priv = dev_get_priv(dev); + u32 value; + + regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value); + + return value; +} + +static int xilinx_timer_probe(struct udevice *dev) +{ + struct xilinx_timer_priv *priv = dev_get_priv(dev); + int ret; + + /* uc_priv->clock_rate has already clock rate */ + ret = regmap_init_mem(dev_ofnode(dev), &priv->regs); + if (ret) { + dev_dbg(dev, "failed to get regbase of timer\n"); + return ret; + } + + regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0); + regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET); + regmap_write(priv->regs, TIMER_CONTROL_OFFSET, + TIMER_ENABLE | TIMER_RELOAD); + + return 0; +} + +static const struct timer_ops xilinx_timer_ops = { + .get_count = xilinx_timer_get_count, +}; + +static const struct udevice_id xilinx_timer_ids[] = { + { .compatible = "xlnx,xps-timer-1.00.a" }, + {} +}; + +U_BOOT_DRIVER(xilinx_timer) = { + .name = "xilinx_timer", + .id = UCLASS_TIMER, + .of_match = xilinx_timer_ids, + .priv_auto = sizeof(struct xilinx_timer_priv), + .probe = xilinx_timer_probe, + .ops = &xilinx_timer_ops, +}; -- 2.36.1