From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [RFC PATCH V2 4/4] Utilize the vmx preemption timer for tsc deadline timer Date: Mon, 6 Jun 2016 15:49:12 +0200 Message-ID: <6c1c1467-5b5b-85e6-7c73-f1d884135871@redhat.com> References: <1464128852-14138-1-git-send-email-yunhong.jiang@linux.intel.com> <1464128852-14138-5-git-send-email-yunhong.jiang@linux.intel.com> <4d3a7b46-f663-92f0-8d3d-d95cf9aa10f2@redhat.com> <20160603172450.6e1d7bcb@jnakajim-build> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: kvm@vger.kernel.org, mtosatti@redhat.com, rkrcmar@redhat.com, kernellwp@gmail.com To: yunhong jiang Return-path: Received: from mx1.redhat.com ([209.132.183.28]:36313 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750764AbcFFNtT (ORCPT ); Mon, 6 Jun 2016 09:49:19 -0400 In-Reply-To: <20160603172450.6e1d7bcb@jnakajim-build> Sender: kvm-owner@vger.kernel.org List-ID: On 04/06/2016 02:24, yunhong jiang wrote: >> > 2) if possible, I would like to remove kvm_lapic_arm_hv_timer. >> > Instead, make switch_to_hv_lapic_timer and start_apic_timer can call >> > kvm_x86_ops->set_hv_timer, passing the desired *guest* TSC. >> > set_hv_timer can convert the guest TSC to a host TSC and save the >> > desired host TSC in struct vmx_vcpu. vcpu_run checks if there is a > Hi, Paolo, I mostly finished my patch, but one thing come to my mind in > the last minutes and hope to get your input. > One issue to save the host TSC on the vmx_vcpu is, if the vCPU thread > is migrated to another pCPU, and the TSC are not synchronized between > these two pCPUs, then the result is not accurate. In previous patchset, > it's ok because we do the calculation on the vcpu_run() thus the > migration does not matter. My suggestion here is to redo the vmx_set_hv_timer in vmx_vcpu_load. It should fix the 32-bit overflow below, too. Paolo > This also bring a tricky situation considering the VMX preepmtion timer > can only hold 32bit value. In a rare situation, the host delta TSC is > less than 32 bit, however, if there is a host tsc backwards after the > migration, then the delta TSC on the new CPU may be larger than 32 bit, > but we can't switch back to sw timer anymore because it's too late. I > add some hacky code on the kvm_arch_vcpu_load(), not sure if it's ok. > > I will send a RFC patch. I'm still looking for a > platform with TSC scaling support, thus not test TSC scaling > yet. Others has been tested. >