From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Date: Mon, 27 May 2019 14:48:09 +0800 Subject: [U-Boot] [PATCH 3/3] rockchip: clk: rk3399: allow requests for all UART clocks In-Reply-To: <20190507085844.49172-3-christoph.muellner@theobroma-systems.com> References: <20190507085844.49172-1-christoph.muellner@theobroma-systems.com> <20190507085844.49172-3-christoph.muellner@theobroma-systems.com> Message-ID: <6d1bf815-8318-42dd-b971-64d9338daf29@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/07/2019 04:58 PM, Christoph Muellner wrote: > This patch adds the rate for UART1 and UART3 the same way > as already implemented for UART0 and UART2. > > This is required for boards, which have their console output > on these UARTs. > > Signed-off-by: Christoph Muellner Reviewed-by: Kever Yang Thanks, - Kever > --- > > drivers/clk/rockchip/clk_rk3399.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c > index 93a652e5ff..aa6a8ad1c9 100644 > --- a/drivers/clk/rockchip/clk_rk3399.c > +++ b/drivers/clk/rockchip/clk_rk3399.c > @@ -912,7 +912,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) > rate = rk3399_spi_get_clk(priv->cru, clk->id); > break; > case SCLK_UART0: > + case SCLK_UART1: > case SCLK_UART2: > + case SCLK_UART3: > return 24000000; > break; > case PCLK_HDMI_CTRL: