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Mon, 22 Nov 2021 08:48:57 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A9011100038; Mon, 22 Nov 2021 08:48:56 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A155B217B92; Mon, 22 Nov 2021 08:48:56 +0100 (CET) Received: from lmecxl0573.lme.st.com (10.75.127.47) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Mon, 22 Nov 2021 08:48:56 +0100 Subject: Re: [PATCH 1/3] stm32mp1: ram: add read valid training support To: Patrick Delaunay , CC: U-Boot STM32 References: <20211115153214.1.I1a0a5850a0ac39ae33620ed14822892c394b1a98@changeid> From: Patrice CHOTARD Message-ID: <6e6b614b-e4dc-1b96-60b3-3b72a6c71a6e@foss.st.com> Date: Mon, 22 Nov 2021 08:48:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211115153214.1.I1a0a5850a0ac39ae33620ed14822892c394b1a98@changeid> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-22_03,2021-11-22_01,2020-04-07_01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Patrick On 11/15/21 3:32 PM, Patrick Delaunay wrote: > Add the read data eye training = training for optimal read valid placement > (RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3. > > This training is supported on the PUBL integrated in the STM32MP15x > DDR subsystem and it is not required for DDR3. > > Signed-off-by: Patrick Delaunay > --- > > drivers/ram/stm32mp1/stm32mp1_ddr.c | 8 ++++++-- > drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c > index 0457166b12..1f8422518b 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c > +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c > @@ -826,8 +826,12 @@ start: > */ > > /* 10. configure PUBL PIR register to specify which training step to run */ > - /* warning : RVTRN is not supported by this PUBL */ > - stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); > + /* RVTRN is excuted only on LPDDR2/LPDDR3 */ > + if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) > + pir = DDRPHYC_PIR_QSTRN; > + else > + pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN; > + stm32mp1_ddrphy_init(priv->phy, pir); > > /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ > ddrphy_idone_wait(priv->phy); > diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > index 3c8885a965..ada3087328 100644 > --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h > @@ -309,6 +309,7 @@ struct stm32mp1_ddrphy { > #define DDRPHYC_PIR_DRAMRST BIT(5) > #define DDRPHYC_PIR_DRAMINIT BIT(6) > #define DDRPHYC_PIR_QSTRN BIT(7) > +#define DDRPHYC_PIR_RVTRN BIT(8) > #define DDRPHYC_PIR_ICPC BIT(16) > #define DDRPHYC_PIR_ZCALBYP BIT(30) > #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) > Reviewed-by: Patrice Chotard Thanks Patrice