From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Vincenzo Frascino <vincenzo.frascino@arm.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com Cc: Andrew Morton <akpm@linux-foundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>, Andrey Ryabinin <aryabinin@virtuozzo.com>, Alexander Potapenko <glider@google.com>, Marco Elver <elver@google.com>, Evgenii Stepanov <eugenis@google.com>, Branislav Rankov <Branislav.Rankov@arm.com>, Andrey Konovalov <andreyknvl@gmail.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Subject: Re: [PATCH 3/5] arm64: mte: CPU feature detection for Asymm MTE Date: Mon, 20 Sep 2021 16:41:56 +0100 [thread overview] Message-ID: <6e6fb454-886e-95ff-fad2-d003a594acbd@arm.com> (raw) In-Reply-To: <20210913081424.48613-4-vincenzo.frascino@arm.com> On 13/09/2021 09:14, Vincenzo Frascino wrote: > Add the cpufeature entries to detect the presence of Asymmetric MTE. > > Note: The tag checking mode is initialized via cpu_enable_mte() -> > kasan_init_hw_tags() hence to enable it we require asymmetric mode > to be at least on the boot CPU. If the boot CPU does not have it, it is > fine for late CPUs to have it as long as the feature is not enabled > (ARM64_CPUCAP_BOOT_CPU_FEATURE). > > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> > --- > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..a18774071a45 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2317,6 +2317,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .sign = FTR_UNSIGNED, > .cpu_enable = cpu_enable_mte, > }, > + { > + .desc = "Asymmetric Memory Tagging Extension", > + .capability = ARM64_MTE_ASYMM, > + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, FWIW, the selected type works for the described use case. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > + .matches = has_cpuid_feature, > + .sys_reg = SYS_ID_AA64PFR1_EL1, > + .field_pos = ID_AA64PFR1_MTE_SHIFT, > + .min_field_value = ID_AA64PFR1_MTE_ASYMM, > + .sign = FTR_UNSIGNED, > + }, > #endif /* CONFIG_ARM64_MTE */ > { > .desc = "RCpc load-acquire (LDAPR)", > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..74a569bf52d6 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -39,6 +39,7 @@ HW_DBM > KVM_PROTECTED_MODE > MISMATCHED_CACHE_TYPE > MTE > +MTE_ASYMM > SPECTRE_V2 > SPECTRE_V3A > SPECTRE_V4 >
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: Vincenzo Frascino <vincenzo.frascino@arm.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com Cc: Andrew Morton <akpm@linux-foundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>, Andrey Ryabinin <aryabinin@virtuozzo.com>, Alexander Potapenko <glider@google.com>, Marco Elver <elver@google.com>, Evgenii Stepanov <eugenis@google.com>, Branislav Rankov <Branislav.Rankov@arm.com>, Andrey Konovalov <andreyknvl@gmail.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Subject: Re: [PATCH 3/5] arm64: mte: CPU feature detection for Asymm MTE Date: Mon, 20 Sep 2021 16:41:56 +0100 [thread overview] Message-ID: <6e6fb454-886e-95ff-fad2-d003a594acbd@arm.com> (raw) In-Reply-To: <20210913081424.48613-4-vincenzo.frascino@arm.com> On 13/09/2021 09:14, Vincenzo Frascino wrote: > Add the cpufeature entries to detect the presence of Asymmetric MTE. > > Note: The tag checking mode is initialized via cpu_enable_mte() -> > kasan_init_hw_tags() hence to enable it we require asymmetric mode > to be at least on the boot CPU. If the boot CPU does not have it, it is > fine for late CPUs to have it as long as the feature is not enabled > (ARM64_CPUCAP_BOOT_CPU_FEATURE). > > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com> > --- > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 2 files changed, 11 insertions(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f8a3067d10c6..a18774071a45 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2317,6 +2317,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .sign = FTR_UNSIGNED, > .cpu_enable = cpu_enable_mte, > }, > + { > + .desc = "Asymmetric Memory Tagging Extension", > + .capability = ARM64_MTE_ASYMM, > + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, FWIW, the selected type works for the described use case. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> > + .matches = has_cpuid_feature, > + .sys_reg = SYS_ID_AA64PFR1_EL1, > + .field_pos = ID_AA64PFR1_MTE_SHIFT, > + .min_field_value = ID_AA64PFR1_MTE_ASYMM, > + .sign = FTR_UNSIGNED, > + }, > #endif /* CONFIG_ARM64_MTE */ > { > .desc = "RCpc load-acquire (LDAPR)", > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..74a569bf52d6 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -39,6 +39,7 @@ HW_DBM > KVM_PROTECTED_MODE > MISMATCHED_CACHE_TYPE > MTE > +MTE_ASYMM > SPECTRE_V2 > SPECTRE_V3A > SPECTRE_V4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-20 15:42 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-13 8:14 [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-13 8:14 ` [PATCH 1/5] kasan: Remove duplicate of kasan_flag_async Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-20 15:31 ` Catalin Marinas 2021-09-20 15:31 ` Catalin Marinas 2021-10-03 17:12 ` Andrey Konovalov 2021-10-03 17:12 ` Andrey Konovalov 2021-09-13 8:14 ` [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-20 15:31 ` Catalin Marinas 2021-09-20 15:31 ` Catalin Marinas 2021-09-13 8:14 ` [PATCH 3/5] arm64: mte: CPU feature detection " Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-20 15:31 ` Catalin Marinas 2021-09-20 15:31 ` Catalin Marinas 2021-09-20 15:41 ` Suzuki K Poulose [this message] 2021-09-20 15:41 ` Suzuki K Poulose 2021-09-13 8:14 ` [PATCH 4/5] arm64: mte: Add asymmetric mode support Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-20 15:31 ` Catalin Marinas 2021-09-20 15:31 ` Catalin Marinas 2021-10-03 17:15 ` Andrey Konovalov 2021-10-03 17:15 ` Andrey Konovalov 2021-10-04 15:39 ` Vincenzo Frascino 2021-10-04 15:39 ` Vincenzo Frascino 2021-09-13 8:14 ` [PATCH 5/5] kasan: Extend KASAN mode kernel parameter Vincenzo Frascino 2021-09-13 8:14 ` Vincenzo Frascino 2021-09-16 10:43 ` Marco Elver 2021-09-16 10:43 ` Marco Elver 2021-09-20 7:46 ` Vincenzo Frascino 2021-09-20 7:46 ` Vincenzo Frascino 2021-10-03 17:16 ` Andrey Konovalov 2021-10-03 17:16 ` Andrey Konovalov 2021-10-04 15:45 ` Vincenzo Frascino 2021-10-04 15:45 ` Vincenzo Frascino 2021-09-20 15:32 ` Catalin Marinas 2021-09-20 15:32 ` Catalin Marinas 2021-09-20 21:29 ` [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Peter Collingbourne 2021-09-20 21:29 ` Peter Collingbourne 2021-09-21 7:03 ` Vincenzo Frascino 2021-09-21 7:03 ` Vincenzo Frascino 2021-09-29 15:49 ` Will Deacon 2021-09-29 15:49 ` Will Deacon 2021-10-04 15:16 ` Vincenzo Frascino 2021-10-04 15:16 ` Vincenzo Frascino
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