From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH 2/2] ARM: imx_v6_v7_defconfig: enable PCI_MSI To: Jingoo Han , 'Tim Harvey' , 'Joao Pinto' References: <1448902811-11399-1-git-send-email-l.stach@pengutronix.de> <1448902811-11399-2-git-send-email-l.stach@pengutronix.de> <1460708469.22710.4.camel@pengutronix.de> <001c01d2ad85$b06af1a0$1140d4e0$@gmail.com> From: Joao Pinto Message-ID: <6eb58d54-b6e8-b709-c7f9-fa19d52cd492@synopsys.com> Date: Wed, 5 Apr 2017 13:07:21 +0100 MIME-Version: 1.0 In-Reply-To: <001c01d2ad85$b06af1a0$1140d4e0$@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, patchwork-lst@pengutronix.de, =?UTF-8?Q?'Krzysztof_Ha=c5=82asa'?= , 'Sascha Hauer' , 'Shawn Guo' , linux-arm-kernel@lists.infradead.org, 'Lucas Stach' Content-Type: text/plain; charset="utf-8" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: w4BzIDk6NTQgUE0gZGUgNC80LzIwMTcsIEppbmdvbyBIYW4gZXNjcmV2ZXU6Cj4gT24gRnJpZGF5 LCBNYXJjaCAzMSwgMjAxNyAxMjowNSBQTSwgVGltIEhhcnZleSB3cm90ZToKPj4gT24gVGh1LCBN YXIgMzAsIDIwMTcgYXQgNDo0MiBQTSwgVGltIEhhcnZleSA8dGhhcnZleUBnYXRld29ya3MuY29t PiB3cm90ZToKPj4+IE9uIEZyaSwgQXByIDE1LCAyMDE2IGF0IDE6MjEgQU0sIEx1Y2FzIFN0YWNo IDxsLnN0YWNoQHBlbmd1dHJvbml4LmRlPgo+PiB3cm90ZToKPj4+PiBBbSBEb25uZXJzdGFnLCBk ZW4gMTQuMDQuMjAxNiwgMDg6MTMgLTA3MDAgc2NocmllYiBUaW0gSGFydmV5Ogo+Pj4+PiBPbiBN b24sIE5vdiAzMCwgMjAxNSBhdCA5OjAwIEFNLCBMdWNhcyBTdGFjaCA8bC5zdGFjaEBwZW5ndXRy b25peC5kZT4KPj4gd3JvdGU6Cj4+Pj4+PiBUaGlzIGhhcyBiZWVuIHN0YWJsZSBvbiBpLk1YNiBm b3IgYSBnb29kIHdoaWxlIG5vdyBhbmQgdGhlcmUgaXMgbm8KPj4+Pj4+IHJlYXNvbiB0byBrZWVw IGl0IGRpc2FibGVkLCBhcyBpdCBhbGxvd3MgdG8gYWxsb2NhdGUgbm9uLXNoYXJlZAo+Pj4+Pj4g SVJRcyBpZiBzZXZlcmFsIFBDSWUgZGV2aWNlcyBhcmUgY29ubmVjdGVkIHRvIGEgc2luZ2xlIGhv c3QuCj4+Pj4+Pgo+Pj4+Pj4gU2lnbmVkLW9mZi1ieTogTHVjYXMgU3RhY2ggPGwuc3RhY2hAcGVu Z3V0cm9uaXguZGU+Cj4+Pj4+PiAtLS0KPj4+Pj4+ICBhcmNoL2FybS9jb25maWdzL2lteF92Nl92 N19kZWZjb25maWcgfCAxICsKPj4+Pj4+ICAxIGZpbGUgY2hhbmdlZCwgMSBpbnNlcnRpb24oKykK Pj4+Pj4+Cj4+Pj4+PiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vY29uZmlncy9pbXhfdjZfdjdfZGVm Y29uZmlnCj4+IGIvYXJjaC9hcm0vY29uZmlncy9pbXhfdjZfdjdfZGVmY29uZmlnCj4+Pj4+PiBp bmRleCA0MTg3ZjY5ZjY2MzAuLmUyY2U2MGQwMGU4YSAxMDA2NDQKPj4+Pj4+IC0tLSBhL2FyY2gv YXJtL2NvbmZpZ3MvaW14X3Y2X3Y3X2RlZmNvbmZpZwo+Pj4+Pj4gKysrIGIvYXJjaC9hcm0vY29u Zmlncy9pbXhfdjZfdjdfZGVmY29uZmlnCj4+Pj4+PiBAQCAtNDUsNiArNDUsNyBAQCBDT05GSUdf U09DX0lNWDdEPXkKPj4+Pj4+ICBDT05GSUdfU09DX0xTMTAyMUE9eQo+Pj4+Pj4gIENPTkZJR19T T0NfVkY2MTA9eQo+Pj4+Pj4gIENPTkZJR19QQ0k9eQo+Pj4+Pj4gK0NPTkZJR19QQ0lfTVNJPXkK Pj4+Pj4+ICBDT05GSUdfUENJX0lNWDY9eQo+Pj4+Pj4gIENPTkZJR19TTVA9eQo+Pj4+Pj4gIENP TkZJR19QUkVFTVBUX1ZPTFVOVEFSWT15Cj4+Pj4+PiAtLQo+Pj4+Pj4gMi42LjIKPj4+Pj4+Cj4+ Pj4+Pgo+Pj4+Pj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KPj4+Pj4+IGxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0Cj4+Pj4+PiBsaW51eC1hcm0t a2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKPj4+Pj4+IGh0dHBzOi8vdXJsZGVmZW5zZS5wcm9v ZnBvaW50LmNvbS92Mi91cmw/dT1odHRwLTNBX19saXN0cy5pbmZyYWRlYWQub3JnX21haWxtYW5f bGlzdGluZm9fbGludXgtMkRhcm0tMkRrZXJuZWwmZD1Ed0lDYVEmYz1EUEw2X1hfNkprWEZ4N0FY V3FCMHRnJnI9czJmTzBoaWkwT0dOT3Y5cVF5X0hSWHkteEFKVUQxTk5vRWNjM2lvX2t4MCZtPXlR eDd5YnUtSkdjUFBoNlpsUXl4a0M2X1V3NjJjdUJLTGI3bzN6cEs3aFEmcz1vLXRSMG1aNXlLTlRU WEtYMU1SN051RExwSGZ2U0hJanppNDdZTHVlMGFBJmU9IAo+Pj4+Pgo+Pj4+PiBMdWNhcywKPj4+ Pj4KPj4+Pj4gQW55IHRob3VnaHRzIG9uIHdoeSBlbmFibGluZyBNU0kgb24gSU1YNiBicmVha3Mg bGVnYWN5IGludGVycnVwdHM/Cj4+Pj4+Cj4+Pj4+IEFnYWluLCBtYW55IFBDSSBkZXZpY2VzL2Ry aXZlcnMgZG9uJ3Qgc3VwcG9ydCBNU0kgYW5kIHRodXMgZW5hYmxpbmcKPj4+Pj4gTVNJIGFzIHRo aXMgcGF0Y2ggZG9lcyBtYWtlcyB0aGlzIGNvbmZpZyBicmVhayBtYW55IFBDSSBkZXZpY2VzIG9u Cj4+Pj4+IElNWDYuCj4+Pj4+Cj4+Pj4+IEkgaGF2ZSBmb3VuZCB0aGF0IE1TSSBkb2VzIGluZGVl ZCB3b3JrIG9uIHRoZSBJTVg2IGZvciBjYXJkcy9kcml2ZXJzCj4+Pj4+IHRoYXQgdXNlIE1TSSwg YnV0IGZvciB0aG9zZSB0aGF0IGRvbid0IHRoZSBsZWdhY3kgaW50ZXJydXB0cyBuZXZlcgo+Pj4+ PiBmaXJlIHJlZ2FyZGxlc3Mgb2YgZ29pbmcgdGhyb3VnaCBhIGJyaWRnZSBvciBkaXJlY3RseSBo YW5naW5nIG9mZiB0aGUKPj4+Pj4gSU1YNi4gSSBhc3N1bWUgeW91IGNhbiBjb25maXJtIHRoaXMg b24geW91ciBib2FyZHMvZGV2aWNlcyBhcyB3ZWxsPwo+Pj4+Pgo+Pj4+IE5vLCB0aGlzIHNlZW1z IHRvIGJlIGFuIGVycmF0YSBpbiB0aGUgRFcgUENJZSBjb3JlLiBUaGUgbWFudWFsIHN0YXRlcwo+ Pj4+IHRoYXQgbGVnYWN5IElSUXMgYW5kIE1TSXMgY2FuJ3QgYmUgdXNlZCB0b2dldGhlciwgYnV0 IEkgdGhvdWdodCB0aGlzCj4+Pj4gb25seSBhcHBsaWVzIHRvIHRoZSBFUCBwYXJ0IG9mIHRoZSBj b3JlLgo+Pj4+Cj4+Pj4gV2UgY2FuIHByb2JhYmx5IGZpeCB0aGUgc2ltcGxlIGNvbmZpZ3VyYXRp b24gYnkgbm90IGVuYWJsaW5nIE1TSQo+PiBzdXBwb3J0Cj4+Pj4gdW50aWwgc29tZW9uZSBhY3R1 YWxseSByZXF1ZXN0cyB0byBzZXQgdXAgYW4gTVNJIElSUSwgc28gYm90aCBJUlEgdHlwZXMKPj4+ PiB3b3JrIHdoZW4gb25seSBvbmUgRVAgaXMgY29ubmVjdGVkLgo+Pj4+IEkgZG9uJ3QgaGF2ZSBh bnkgaWRlYSB5ZXQgaG93IHRvIGZpeCBzZXR1cHMgd2l0aCBhIFBDSWUgc3dpdGNoIHdoZXJlCj4+ Pj4gc29tZSBjb25uZWN0ZWQgRVBzIG1pZ2h0IGxpa2UgdG8gdXNlIE1TSXMgd2hpbGUgc29tZSBv dGhlcnMgY2FuJ3QgdXNlCj4+Pj4gdGhlbS4KPj4+Pgo+Pj4+IFJlZ2FyZHMsCj4+Pj4gTHVjYXMK Pj4+Pgo+Pj4KPj4+IEx1Y2FzLAo+Pj4KPj4+IEkgZmVlbCBhIGJpdCBkdW1iIGhlcmUgZm9yIGZv cmdldHRpbmcgYWJvdXQgdGhpcyBpc3N1ZSBhbmQgbGV0dGluZyBpdAo+Pj4gZHJvcCwgYnV0IEkn dmUganVzdCBzcGVudCBhIGRheSBkZWJ1Z2dpbmcgYW4gaXNzdWUgd2l0aCB0aGUgYXRoOWsKPj4+ IHdpcmVsZXNzIGRyaXZlciBvbmx5IHRvIHJlYWxpemUgaXQgd2FzIHRoYXQgdGhlIGF0aDlrIGNh cmQgYW5kL29yCj4+PiBkcml2ZXIgZG9lc24ndCBzdXBwb3J0IE1TSSBpbnRlcnJ1cHRzIGFuZCB0 aHVzIG5vIGxvbmdlciB3b3JrIG9uCj4+PiBtYWlubGluZSBrZXJuZWxzIHRoYXQgaGF2ZSBNU0kg ZW5hYmxlZC4gVG8gYmUgaG9uZXN0IEknbSBub3Qgc3VyZSBob3cKPj4+IG1hbnkgUENJZSBkZXZp Y2VzIG91dCB0aGVyZSBjYW4ndCBzdXBwb3J0IE1TSSBiZWNhdXNlIG9mIGhhcmR3YXJlCj4+PiBs aW1pdGF0aW9ucyB2cyBkcml2ZXJzIHRoYXQgc2ltcGx5IGhhdmUgbm90IGltcGxlbWVudGVkIGl0 Lgo+Pj4KPj4+IFRvIG1ha2UgbWF0dGVycyB3b3JzZSAzZWU4MDM2NDFlNzZiZWE3NmVjNzMwYzgw ZGNjNjQ3MzlhOTkxOWZmIG1ha2VzCj4+PiBpdCBzdWNoIHRoYXQgeW91IGNhbid0IGRpc2FibGUg TVNJIG9uIHRoZSBJTVg2Lgo+Pj4KPj4+IElzIHRoZXJlIHNvbWUgZml4IHlvdSBjYW4gdGhpbmsg b2YgdG8gbWFrZSB0aGUgSU1YNiBQQ0llIGhvc3QKPj4+IGNvbnRyb2xsZXIgcmFpc2UgYW4gaW50 ZXJydXB0IGZvciBjYXJkcy9kcml2ZXJzIHRoYXQgdXNlIGxlZ2FjeSBpcnEncz8KPj4+IElmIG5v dCwgdGhlbiB3ZSBuZWVkIHRvIGFsbG93IE1TSSB0byBiZSBkaXNhYmxlZCBmb3IgSU1YNiBhbmQg ZGVmYXVsdAo+Pj4gaXQgdG8gZGlzYWJsZWQgZm9yIGNvbXBhdGliaWxpdHkuCj4+Pgo+Pgo+PiBK b2FvIC8gSmluZ29vLAo+Pgo+PiAoQWRkaW5nIGxpbnV4LXBjaSB0byB0aGUgbGlzdCB0byBwaWNr IHVwIG1haW50YWluZXJzIG9mIG90aGVyIERXQyBQQ0llCj4+IGNvcmUgZHJpdmVycykKPj4KPj4g SXMgTHVjYSdzIHN0YXRlbWVudCB0aGF0ICdsZWdhY3kgSVJRcyBhbmQgTVNJcyBjYW4ndCBiZSB1 c2VkIHRvZ2V0aGVyJwo+PiB0cnVlIGluIGdlbmVyYWwgZm9yIHRoZSBEVyBQQ0llIGNvcmU/IElm IGFueSBvZiB0aGUgaG9zdCBjb250cm9sbGVycwo+PiB1c2luZyB0aGlzIGNvcmUgY2FuJ3Qgc3Vw cG9ydCBib3RoIGxlZ2FjeSBhbmQgTVNJIGlycXMgdG9nZXRoZXIgSQo+PiBzdGlsbCBiZWxpZXZl IHdlIHNob3VsZG4ndCBlbmFibGUvcmVxdWlyZSBNU0kgYXMgaXQgYnJlYWtzIGFueQo+PiBjYXJk L2RyaXZlciB0aGF0IG9ubHkgc3VwcG9ydHMgbGVnYWN5IGludGVycnVwdHMgKHN1Y2ggYXMgYXRo OWspLgo+IAo+IElmIHRoZXJlIGFyZSAyIERXIFBDSWUgY29udHJvbGxlcnMsIG9uZSBjb250cm9s bGVyIGNhbiBiZSB1c2VkIGZvciBsZWdhY3kKPiBhbmQgYW5vdGhlciBjb250cm9sbGVyIGNhbiBi ZSB1c2VkIGZvciBNU0kuCj4gCj4gQnV0LCBJIGFtIG5vdCBzdXJlIHRoYXQgb25lIERXIFBDSWUg Y29udHJvbGxlciBjYW4gc3VwcG9ydCBib3RoIE1TSSBkZXZpY2UKPiBhbmQgbGVnYWN5IGludGVy cnVwdCBkZXZpY2UgYXQgdGhlIHNhbWUgdGltZS4KPiAKPiBUbyBKb2FvIFBpbnRvLAo+IFdpbGwg eW91IGNvbmZpcm0gdGhpcz8KPiAKCkhpIEppbmdvbywKSSBjb25maXJtIHRoYXQgaWYgYSBSQyBo YXMgTVNJIGVuYWJsZSwgaXQgd29uJ3Qgc3VwcG9ydCBsZWdhY3kgaW50ZXJydXB0cy4KClJlZ2Fy ZHMsCkpvYW8KCj4gT3IgaWYgdGhlcmUgaXMgYW55b25lIHdobyBrbm93cyB0aGlzIHdlbGwsIHBs ZWFzZSBzaGFyZSB5b3VyIGtub3dsZWRnZS4gOi0pCj4gVGhhbmtzLgo+IAo+IEJlc3QgcmVnYXJk cywKPiBKaW5nb28gSGFuCj4gCj4+Cj4+IFJlZ2FyZHMsCj4+Cj4+IFRpbQo+IAoKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwg bWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8v bGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joao.Pinto@synopsys.com (Joao Pinto) Date: Wed, 5 Apr 2017 13:07:21 +0100 Subject: [PATCH 2/2] ARM: imx_v6_v7_defconfig: enable PCI_MSI In-Reply-To: <001c01d2ad85$b06af1a0$1140d4e0$@gmail.com> References: <1448902811-11399-1-git-send-email-l.stach@pengutronix.de> <1448902811-11399-2-git-send-email-l.stach@pengutronix.de> <1460708469.22710.4.camel@pengutronix.de> <001c01d2ad85$b06af1a0$1140d4e0$@gmail.com> Message-ID: <6eb58d54-b6e8-b709-c7f9-fa19d52cd492@synopsys.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org ?s 9:54 PM de 4/4/2017, Jingoo Han escreveu: > On Friday, March 31, 2017 12:05 PM, Tim Harvey wrote: >> On Thu, Mar 30, 2017 at 4:42 PM, Tim Harvey wrote: >>> On Fri, Apr 15, 2016 at 1:21 AM, Lucas Stach >> wrote: >>>> Am Donnerstag, den 14.04.2016, 08:13 -0700 schrieb Tim Harvey: >>>>> On Mon, Nov 30, 2015 at 9:00 AM, Lucas Stach >> wrote: >>>>>> This has been stable on i.MX6 for a good while now and there is no >>>>>> reason to keep it disabled, as it allows to allocate non-shared >>>>>> IRQs if several PCIe devices are connected to a single host. >>>>>> >>>>>> Signed-off-by: Lucas Stach >>>>>> --- >>>>>> arch/arm/configs/imx_v6_v7_defconfig | 1 + >>>>>> 1 file changed, 1 insertion(+) >>>>>> >>>>>> diff --git a/arch/arm/configs/imx_v6_v7_defconfig >> b/arch/arm/configs/imx_v6_v7_defconfig >>>>>> index 4187f69f6630..e2ce60d00e8a 100644 >>>>>> --- a/arch/arm/configs/imx_v6_v7_defconfig >>>>>> +++ b/arch/arm/configs/imx_v6_v7_defconfig >>>>>> @@ -45,6 +45,7 @@ CONFIG_SOC_IMX7D=y >>>>>> CONFIG_SOC_LS1021A=y >>>>>> CONFIG_SOC_VF610=y >>>>>> CONFIG_PCI=y >>>>>> +CONFIG_PCI_MSI=y >>>>>> CONFIG_PCI_IMX6=y >>>>>> CONFIG_SMP=y >>>>>> CONFIG_PREEMPT_VOLUNTARY=y >>>>>> -- >>>>>> 2.6.2 >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> linux-arm-kernel mailing list >>>>>> linux-arm-kernel at lists.infradead.org >>>>>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_mailman_listinfo_linux-2Darm-2Dkernel&d=DwICaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=yQx7ybu-JGcPPh6ZlQyxkC6_Uw62cuBKLb7o3zpK7hQ&s=o-tR0mZ5yKNTTXKX1MR7NuDLpHfvSHIjzi47YLue0aA&e= >>>>> >>>>> Lucas, >>>>> >>>>> Any thoughts on why enabling MSI on IMX6 breaks legacy interrupts? >>>>> >>>>> Again, many PCI devices/drivers don't support MSI and thus enabling >>>>> MSI as this patch does makes this config break many PCI devices on >>>>> IMX6. >>>>> >>>>> I have found that MSI does indeed work on the IMX6 for cards/drivers >>>>> that use MSI, but for those that don't the legacy interrupts never >>>>> fire regardless of going through a bridge or directly hanging off the >>>>> IMX6. I assume you can confirm this on your boards/devices as well? >>>>> >>>> No, this seems to be an errata in the DW PCIe core. The manual states >>>> that legacy IRQs and MSIs can't be used together, but I thought this >>>> only applies to the EP part of the core. >>>> >>>> We can probably fix the simple configuration by not enabling MSI >> support >>>> until someone actually requests to set up an MSI IRQ, so both IRQ types >>>> work when only one EP is connected. >>>> I don't have any idea yet how to fix setups with a PCIe switch where >>>> some connected EPs might like to use MSIs while some others can't use >>>> them. >>>> >>>> Regards, >>>> Lucas >>>> >>> >>> Lucas, >>> >>> I feel a bit dumb here for forgetting about this issue and letting it >>> drop, but I've just spent a day debugging an issue with the ath9k >>> wireless driver only to realize it was that the ath9k card and/or >>> driver doesn't support MSI interrupts and thus no longer work on >>> mainline kernels that have MSI enabled. To be honest I'm not sure how >>> many PCIe devices out there can't support MSI because of hardware >>> limitations vs drivers that simply have not implemented it. >>> >>> To make matters worse 3ee803641e76bea76ec730c80dcc64739a9919ff makes >>> it such that you can't disable MSI on the IMX6. >>> >>> Is there some fix you can think of to make the IMX6 PCIe host >>> controller raise an interrupt for cards/drivers that use legacy irq's? >>> If not, then we need to allow MSI to be disabled for IMX6 and default >>> it to disabled for compatibility. >>> >> >> Joao / Jingoo, >> >> (Adding linux-pci to the list to pick up maintainers of other DWC PCIe >> core drivers) >> >> Is Luca's statement that 'legacy IRQs and MSIs can't be used together' >> true in general for the DW PCIe core? If any of the host controllers >> using this core can't support both legacy and MSI irqs together I >> still believe we shouldn't enable/require MSI as it breaks any >> card/driver that only supports legacy interrupts (such as ath9k). > > If there are 2 DW PCIe controllers, one controller can be used for legacy > and another controller can be used for MSI. > > But, I am not sure that one DW PCIe controller can support both MSI device > and legacy interrupt device at the same time. > > To Joao Pinto, > Will you confirm this? > Hi Jingoo, I confirm that if a RC has MSI enable, it won't support legacy interrupts. Regards, Joao > Or if there is anyone who knows this well, please share your knowledge. :-) > Thanks. > > Best regards, > Jingoo Han > >> >> Regards, >> >> Tim >