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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id jz18-20020a17090775f200b0070fd7da3e47sm8859460ejc.127.2022.06.30.03.07.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Jun 2022 03:07:03 -0700 (PDT) Message-ID: <6fafbed8-9c6d-ae1b-c613-44982b681276@linaro.org> Date: Thu, 30 Jun 2022 12:07:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 1/4] dt-bindings: misc: tmr-manager: Add device-tree binding for TMR Manager Content-Language: en-US To: "Rao, Appana Durga Kedareswara" , "Simek, Michal" , Appana Durga Kedareswara rao , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "michal.simek@xilinx.com" , "derek.kiernan@xilinx.com" , "dragan.cvetic@xilinx.com" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "linux-arm-kernel@lists.infradead.org" Cc: "git (AMD-Xilinx)" , "git@xilinx.com" References: <20220628054338.1631516-1-appana.durga.rao@xilinx.com> <20220628054338.1631516-2-appana.durga.rao@xilinx.com> <6f5a1b1e-b484-3a15-00be-2c1ddc09468e@amd.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/06/2022 14:37, Rao, Appana Durga Kedareswara wrote: > Hi, > > > On 29/06/22 5:29 pm, Michal Simek wrote: >> >> >> On 6/29/22 13:45, Krzysztof Kozlowski wrote: >>> On 29/06/2022 13:23, Michal Simek wrote: >>>> >>>> >>>> On 6/29/22 12:07, Krzysztof Kozlowski wrote: >>>>> On 28/06/2022 07:43, Appana Durga Kedareswara rao wrote: >>>>>> This commit adds documentation for Triple Modular Redundancy(TMR) >>>>>> Manager >>>>>> IP. The Triple Modular Redundancy(TMR) Manager is responsible for >>>>>> handling >>>>>> the TMR subsystem state, including fault detection and error recovery >>>>>> provides soft error detection, correction and recovery features. >>>>>> >>>>>> Signed-off-by: Appana Durga Kedareswara rao >>>>>> >>>>>> --- >>>>>> .../bindings/misc/xlnx,tmr-manager.yaml | 48 >>>>>> +++++++++++++++++++ >>>>> >>>>> This is not a misc device. Find appropriate subsystem for it. It's not >>>>> EDAC, right? >>>> >>>> We were thinking where to put it but it is not EDAC driver. >>>> If you have better suggestion for subsystem please let us know. >>> >>> I don't know what's the device about. The description does not help: >>> >>> "TMR Manager is responsible for TMR subsystem state..." >> >> ok. let's improve commit message in v2. > > Sure will improve the commit message in v2. >> >> TMR - triple module redundancy. >> >> You design the system with one CPU which is default microblaze >> configuration with interrupt controller, timer and other IPs. >> >> And then say I want to do it triple redundant with all that voting, etc. >> If you want to get all details you can take a look at this guide >> >> https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/tmr/v1_0/pg268-tmr.pdf >> >> >> In short TMR manager is servicing all that 3 cores and making sure that >> they are all running in sync. If not it has capability recover the >> system. It means cpu gets to break handler (it is the part of microblaze >> series) and it restarts all cpus. >> >> And TMR inject driver is module which is capable to inject error to >> internal memory to cause the exception to exercise that recovery code. >> >> Kedar: Feel free to correct me or add more details. > > Thanks Michal for the detailed explanation. > > The Triple Modular Redundancy(TMR) subsystem has three Microblaze > processor instances, If any one of the Microblaze processors goes to an > unknown state due to fault injection break handler will get called, > which in turn calls the tmr manager driver API to perform recovery. > like Michal said TMR inject driver is capable of inject error to > internal memory to cause fault in one the Microblaze processor > > @Krzysztof : please let me know if more information required about > this TMR subsystem will provide. Some features sound like watchdog. If it was ARM, I would suggest to put it under "soc". Is a term System-on-Chip applicable to Microblaze? Other option is to store it under microblaze (although for ARM and RISC-V this is actually discouraged in favor of soc). Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48FD0C433EF for ; Thu, 30 Jun 2022 10:08:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/PjwyyVWH+ZwCYqa8eqdb8JKrUnzezs63a/9bjiNV/c=; b=FFCS0T/x4c0Xoj KDs5DL01lzT8IRi+v3BWpUK2spGamDXA0/ZrSYi+qI90GIr7sT1dCP6BQ4LJHk0bFo8q6Pbl7F5Ex cN860ZwScJKXT5/b+8pEN4vVgvJq6jfwIy8GYmVGRbJ5Koo0n6/2uMHHCMdTQJj8S5P1vIDsUoAX3 nRilk69z4H7MLBqeO4eDWRnoASxkaKFx5xIPouPsoNo2K/B3d0DoO7wUmhn5WwmNumpJo6WAS6RIP hP7KIsxbLvhKXDn74Zhszuzw4nVaQJszvmJdqTk2R8iZ7hH8fx7Sa4yrH3MC73z3W227X78Sdl8OP 9VQDssl/fN1GFAmFLUtw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6r4r-00GSJN-Ay; Thu, 30 Jun 2022 10:07:13 +0000 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6r4l-00GSHO-Vu for linux-arm-kernel@lists.infradead.org; Thu, 30 Jun 2022 10:07:11 +0000 Received: by mail-ed1-x52e.google.com with SMTP id ej4so25862692edb.7 for ; Thu, 30 Jun 2022 03:07:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=QiZFE3NY4GpzbWqcVyfbAnOQf74waO1WZQ6maNc0JPw=; b=eo3tpQhml3zuLS6EMetDbiMihtcGUCI0LuemTL7CehN2ehr/usuoPH5bwJZgtW6Dbj hHhi8hchNa20ttbPTb4C/agoXHVRFnA7C2mNoYAhVgG21xklwR39m3HaNLIAfVgp+O2B HUhU73gt3m0oEw2UlAcQeRZWyEQyKhjMuEsQRoQzO8V+AZHuVzw5jZZs2JKTzFyPfBWe KDqG9UiR+DK+rd7+9BY2eLJNLh/WFrS4F92IWbcyQM5DW5rklklTVjMfjkPo+ldsKte2 XNsnceeVIgLLnGybmTqhOP+2XwLkQmQCYsgTvB68lwEppERccpmnsZ/6zfeUWteWzbCG 5Hxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=QiZFE3NY4GpzbWqcVyfbAnOQf74waO1WZQ6maNc0JPw=; b=mRRiBONT7AYks7RBcXrdea8adLvxagPir1FEWZxtzI92EEMjkZ18cmwgoWwODx6GbB +vJzzKdUdEv6g2tdU7isFYT1xzXvLJaPLIb/VrA8lHIydxAPpx1ZsP/gj+12l1Y80niy ekxb4hHxkk7+YfLyWPhTQpmW9jwT6jZts/UA6C/AD9TsHSmW4HCVadRrTs4SCrPLkokp ccSiJRhp0MuItvFkT7BiGFvcXxfIEJCX7pslM1RpQLV057bfi0gUWN+j4p8EoTXzstVi Ilh7Dv8e9wALhky735bf3NGnA5z3fXUeoVfCz5Mvsp3BOJe91cx7ue7w9n562j1pI7kE 5Hig== X-Gm-Message-State: AJIora+uyZfU+rdVNqIrgm3PMvVLxCX1xsV5MruKUV7cwirMBgXOdVgK wq956nw+aUvclyWgKAy/S1PVFbBn6qb3mQ== X-Google-Smtp-Source: AGRyM1sRuht+AaZtKiV7wXncnzcPYsM4VrO1Sxs8tTbqxYOin4IohCnFH9E62zxQFeOe/1NdCdXk4w== X-Received: by 2002:aa7:d5c9:0:b0:435:8099:30e6 with SMTP id d9-20020aa7d5c9000000b00435809930e6mr10509066eds.384.1656583624201; Thu, 30 Jun 2022 03:07:04 -0700 (PDT) Received: from [192.168.0.189] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id jz18-20020a17090775f200b0070fd7da3e47sm8859460ejc.127.2022.06.30.03.07.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Jun 2022 03:07:03 -0700 (PDT) Message-ID: <6fafbed8-9c6d-ae1b-c613-44982b681276@linaro.org> Date: Thu, 30 Jun 2022 12:07:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 1/4] dt-bindings: misc: tmr-manager: Add device-tree binding for TMR Manager Content-Language: en-US To: "Rao, Appana Durga Kedareswara" , "Simek, Michal" , Appana Durga Kedareswara rao , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "michal.simek@xilinx.com" , "derek.kiernan@xilinx.com" , "dragan.cvetic@xilinx.com" , "arnd@arndb.de" , "gregkh@linuxfoundation.org" , "linux-arm-kernel@lists.infradead.org" Cc: "git (AMD-Xilinx)" , "git@xilinx.com" References: <20220628054338.1631516-1-appana.durga.rao@xilinx.com> <20220628054338.1631516-2-appana.durga.rao@xilinx.com> <6f5a1b1e-b484-3a15-00be-2c1ddc09468e@amd.com> From: Krzysztof Kozlowski In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220630_030708_080613_FF7A73EA X-CRM114-Status: GOOD ( 22.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 29/06/2022 14:37, Rao, Appana Durga Kedareswara wrote: > Hi, > > > On 29/06/22 5:29 pm, Michal Simek wrote: >> >> >> On 6/29/22 13:45, Krzysztof Kozlowski wrote: >>> On 29/06/2022 13:23, Michal Simek wrote: >>>> >>>> >>>> On 6/29/22 12:07, Krzysztof Kozlowski wrote: >>>>> On 28/06/2022 07:43, Appana Durga Kedareswara rao wrote: >>>>>> This commit adds documentation for Triple Modular Redundancy(TMR) >>>>>> Manager >>>>>> IP. The Triple Modular Redundancy(TMR) Manager is responsible for >>>>>> handling >>>>>> the TMR subsystem state, including fault detection and error recovery >>>>>> provides soft error detection, correction and recovery features. >>>>>> >>>>>> Signed-off-by: Appana Durga Kedareswara rao >>>>>> >>>>>> --- >>>>>> .../bindings/misc/xlnx,tmr-manager.yaml | 48 >>>>>> +++++++++++++++++++ >>>>> >>>>> This is not a misc device. Find appropriate subsystem for it. It's not >>>>> EDAC, right? >>>> >>>> We were thinking where to put it but it is not EDAC driver. >>>> If you have better suggestion for subsystem please let us know. >>> >>> I don't know what's the device about. The description does not help: >>> >>> "TMR Manager is responsible for TMR subsystem state..." >> >> ok. let's improve commit message in v2. > > Sure will improve the commit message in v2. >> >> TMR - triple module redundancy. >> >> You design the system with one CPU which is default microblaze >> configuration with interrupt controller, timer and other IPs. >> >> And then say I want to do it triple redundant with all that voting, etc. >> If you want to get all details you can take a look at this guide >> >> https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/tmr/v1_0/pg268-tmr.pdf >> >> >> In short TMR manager is servicing all that 3 cores and making sure that >> they are all running in sync. If not it has capability recover the >> system. It means cpu gets to break handler (it is the part of microblaze >> series) and it restarts all cpus. >> >> And TMR inject driver is module which is capable to inject error to >> internal memory to cause the exception to exercise that recovery code. >> >> Kedar: Feel free to correct me or add more details. > > Thanks Michal for the detailed explanation. > > The Triple Modular Redundancy(TMR) subsystem has three Microblaze > processor instances, If any one of the Microblaze processors goes to an > unknown state due to fault injection break handler will get called, > which in turn calls the tmr manager driver API to perform recovery. > like Michal said TMR inject driver is capable of inject error to > internal memory to cause fault in one the Microblaze processor > > @Krzysztof : please let me know if more information required about > this TMR subsystem will provide. Some features sound like watchdog. If it was ARM, I would suggest to put it under "soc". Is a term System-on-Chip applicable to Microblaze? Other option is to store it under microblaze (although for ARM and RISC-V this is actually discouraged in favor of soc). Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel