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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id f9sm7137227wrm.48.2021.07.03.09.29.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Jul 2021 09:29:13 -0700 (PDT) Subject: Re: [PATCH 2/6] dp8393x: don't force 32-bit register access To: Mark Cave-Ayland , qemu-devel@nongnu.org References: <20210703141947.352295-1-f4bug@amsat.org> <20210703141947.352295-3-f4bug@amsat.org> <88ef2d9c-7dcb-2e2e-037c-6af306ad2a12@ilande.co.uk> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <6fb1c380-1a0c-9d0e-be20-b2a7baec3f51@amsat.org> Date: Sat, 3 Jul 2021 18:29:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <88ef2d9c-7dcb-2e2e-037c-6af306ad2a12@ilande.co.uk> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Laurent Vivier , Finn Thain Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/3/21 4:39 PM, Mark Cave-Ayland wrote: > On 03/07/2021 15:19, Philippe Mathieu-Daudé wrote: > >> From: Mark Cave-Ayland >> >> Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that >> all accesses >> to the registers were 32-bit but this is actually not the case. The >> access size is >> determined by the CPU instruction used and not the number of physical >> address lines. >> >> The big_endian workaround applied to the register read/writes was >> actually caused >> by forcing the access size to 32-bit when the guest OS was using a >> 16-bit access. >> Since the registers are 16-bit then we can simply set .impl.min_access >> to 2 and >> then the memory API will automatically do the right thing for both >> 16-bit accesses >> used by Linux and 32-bit accesses used by the MacOS toolbox ROM. > > The change should work, but the commit message above needs a slight > tweak - maybe something like this? > > Since the registers are 16-bit then we can simply set both > .impl.min_access and .impl.max_access to 2 and then the memory API will > automatically do the right thing for both 16-bit accesses used by Linux > and 32-bit accesses used by the MacOS toolbox ROM. Do you mind sending v3 of this patch reworded (and including the .valid fields)? >> Signed-off-by: Mark Cave-Ayland >> Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses") >> Tested-by: Finn Thain >> Message-Id: <20210625065401.30170-9-mark.cave-ayland@ilande.co.uk> >> [PMD: dp8393x_ops.impl.max_access_size 4 -> 2] >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   hw/net/dp8393x.c | 9 ++++----- >>   1 file changed, 4 insertions(+), 5 deletions(-)