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Is it necessary to modify >> kms_psr2_su for testing PSR2 manual tracking? > > kms_psr2_su is to test that PSR2 is sending selective updates, just adding a couple of lines we can make it work with selective fetch. > >>> - kms_psr: psr2_*_(mmap_gtt, mmap_cpu, blt and render), all those >>> tests should be dropped or skipped for display 12+. >>> >> Could you explain in more detail why we need to skip on display 12+? > > This are stuff that would end up calling intel_psr_invalidate/flush(). > Thanks for the explanation. And there is an issue confirmed in local tests, so I leave additional comments. >> >>> Signed-off-by: José Roberto de Souza >>> --- >>> drivers/gpu/drm/i915/display/intel_psr.c | 9 --------- >>> drivers/gpu/drm/i915/i915_params.h | 2 +- >>> 2 files changed, 1 insertion(+), 10 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c >>> index 894a2d35668a2..e128f0c2aeecc 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_psr.c >>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c >>> @@ -877,15 +877,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, >>> return false; >>> } >>> >>> -/* >>> - * We are missing the implementation of some workarounds to enabled PSR2 >>> - * in Alderlake_P, until ready PSR2 should be kept disabled. >>> - */ >>> -if (IS_ALDERLAKE_P(dev_priv)) { >>> -drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n"); >>> -return false; >>> -} >>> - >>> if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { >>> drm_dbg_kms(&dev_priv->drm, >>> "PSR2 not supported in transcoder %s\n", >>> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h >>> index f27eceb82c0f5..8d725b64592d8 100644 >>> --- a/drivers/gpu/drm/i915/i915_params.h >>> +++ b/drivers/gpu/drm/i915/i915_params.h >>> @@ -55,7 +55,7 @@ struct drm_printer; >>> param(int, enable_fbc, -1, 0600) \ >>> param(int, enable_psr, -1, 0600) \ >>> param(bool, psr_safest_params, false, 0400) \ >>> -param(bool, enable_psr2_sel_fetch, false, 0400) \ >>> +param(bool, enable_psr2_sel_fetch, true, 0400) \ If we do not modify this part and do not enable it by default at boot time as shown in the original code below, param(bool, enable_psr2_sel_fetch, false, 0400) \ when we execute the kms_psr2_sf test case of igt, the FIFO underrun as below still occurs. i915 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun: port,transcoder, When PSR2 panel is used, PSR1 is enabled by default when enable_psr2_sel_fetch is not enabled by default. And when kms_psr2_sf is executed, the mode is changed to PSR2, and when kms_psr2_sf is terminated, PSR2 is deactivated and PSR1 is re-enabled. At this point. I suspect there is a problem. >>> param(int, disable_power_well, -1, 0400) \ >>> param(int, enable_ips, 1, 0600) \ >>> param(int, invert_brightness, 0, 0600) \ >>> >