From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_HTML_MOSTLY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56706C2BB48 for ; Mon, 14 Dec 2020 18:45:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1426922573 for ; Mon, 14 Dec 2020 18:45:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1426922573 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9315A6E0C9; Mon, 14 Dec 2020 18:45:09 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5BBDA6E0C9; Mon, 14 Dec 2020 18:45:08 +0000 (UTC) IronPort-SDR: W3NlH6TlPhTzQci41cHWji262/ycvCByEBGb4XQoV/mkdM09QE8FBEic6yrpccw8opVV6rcFje SFEAmSoUjoVA== X-IronPort-AV: E=McAfee;i="6000,8403,9834"; a="162505202" X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208,217";a="162505202" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2020 10:45:06 -0800 IronPort-SDR: 5xZweUbirlWjanYrWrjoY5E1P3gdENilyURIA5vkQtH0iqJZci2lSzuxvcuHZfOAPhUgati3rG jVOBaPK+xR0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,420,1599548400"; d="scan'208,217";a="383256032" Received: from orsmsx606.amr.corp.intel.com ([10.22.229.19]) by fmsmga002.fm.intel.com with ESMTP; 14 Dec 2020 10:45:05 -0800 Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 14 Dec 2020 10:45:04 -0800 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 14 Dec 2020 10:45:04 -0800 Received: from orsmsx610.amr.corp.intel.com ([10.22.229.23]) by ORSMSX610.amr.corp.intel.com ([10.22.229.23]) with mapi id 15.01.1713.004; Mon, 14 Dec 2020 10:45:04 -0800 From: "Chang, Yu bruce" To: Chris Wilson , "intel-gfx@lists.freedesktop.org" Thread-Topic: [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture_size() Thread-Index: AQHW0Gtb2Usp9qHUFUmsvUL74KoMQan27y7/ Date: Mon, 14 Dec 2020 18:45:04 +0000 Message-ID: <7021dc5149a24438878f6540a0c4aed8@intel.com> References: <20201212094354.3023502-1-chris@chris-wilson.co.uk> In-Reply-To: <20201212094354.3023502-1-chris@chris-wilson.co.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.132] MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture_size() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "igt-dev@lists.freedesktop.org" Content-Type: multipart/mixed; boundary="===============1014413096==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============1014413096== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_7021dc5149a24438878f6540a0c4aed8intelcom_" --_000_7021dc5149a24438878f6540a0c4aed8intelcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Some minor comments as below. Reviewed-by: Bruce Chang ________________________________ From: Chris Wilson Sent: Saturday, December 12, 2020 1:43 AM To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org; Chris Wilson; Chang, Yu bruce Subject: [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture_size() In order to find the correct aperture size for the test, we want to pass the test's device into the query. Reported-by: Bruce Chang Signed-off-by: Chris Wilson Cc: Bruce Chang --- lib/i915/gem_mman.c | 108 +++++++++++++++++++++++++++ lib/i915/gem_mman.h | 6 ++ lib/ioctl_wrappers.c | 116 ----------------------------- lib/ioctl_wrappers.h | 5 -- tests/i915/gem_concurrent_all.c | 12 +-- tests/i915/gem_mmap.c | 4 +- tests/i915/gem_mmap_gtt.c | 10 +-- tests/i915/gem_pwrite.c | 6 +- tests/i915/gem_shrink.c | 2 +- tests/i915/gem_tiled_fence_blits.c | 2 +- tests/i915/i915_pm_rpm.c | 4 +- tests/kms_big_fb.c | 2 +- tests/kms_flip.c | 2 +- tests/prime_mmap.c | 4 +- 14 files changed, 138 insertions(+), 145 deletions(-) diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c index 93bef2bfc..703c6a5c1 100644 --- a/lib/i915/gem_mman.c +++ b/lib/i915/gem_mman.c @@ -27,7 +27,9 @@ #include #include "igt_core.h" +#include "igt_device.h" #include "ioctl_wrappers.h" +#include "intel_chipset.h" #include "gem_mman.h" @@ -551,3 +553,109 @@ const struct mmap_offset mmap_offset_types[] =3D { { "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC }, {}, }; + +/** + * gem_available_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the available gpu aperture s= ize + * usable in a batchbuffer. + * + * Returns: The available gtt address space size. + */ +uint64_t gem_available_aperture_size(int fd) +{ + struct drm_i915_gem_get_aperture aperture =3D { + aperture.aper_available_size =3D 256*1024*1024, + }; + + ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + errno =3D 0; + + return aperture.aper_available_size; +} + +/** + * gem_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the total gpu aperture size. + * + * Returns: The total gtt address space size. + */ +uint64_t gem_aperture_size(int fd) +{ + struct drm_i915_gem_context_param p =3D { + .param =3D 0x3 + }; Understand this is the original code, but it will be more readable to use I= 915_CONTEXT_PARAM_GTT_SIZE instead of 3. + + if (__gem_context_get_param(fd, &p)) + p.value =3D gem_global_aperture_size(fd); + + return p.value; +} + +/** + * gem_mappable_aperture_size: + * + * Feature test macro to query the kernel for the mappable gpu aperture si= ze. + * This is the area available for GTT memory mappings. + * + * Returns: The mappable gtt address space size. + */ +uint64_t gem_mappable_aperture_size(int fd) +{ + struct pci_device *pci_dev =3D igt_device_get_pci_device(fd); Does it make sense to eliminate the function intel_get_pci_device() if not = being used anymore? But it can be a separate patch. + int bar; + + if (intel_gen(pci_dev->device_id) < 3) + bar =3D 0; + else + bar =3D 2; + + return pci_dev->regions[bar].size; +} + +/** + * gem_global_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the global gpu aperture size= . + * This is the area available for the kernel to perform address translatio= ns. + * + * Returns: The gtt address space size. + */ +uint64_t gem_global_aperture_size(int fd) +{ + struct drm_i915_gem_get_aperture aperture =3D { + aperture.aper_size =3D 256*1024*1024 + }; + + ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + errno =3D 0; + + return aperture.aper_size; +} + +/** + * gem_available_fences: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the number of available fenc= es + * usable in a batchbuffer. Only relevant for pre-gen4. + * + * Returns: The number of available fences. + */ +int gem_available_fences(int fd) +{ + int num_fences =3D 0; + struct drm_i915_getparam gp =3D { + gp.param =3D I915_PARAM_NUM_FENCES_AVAIL, + gp.value =3D &num_fences, + }; + + ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)); + errno =3D 0; + + return num_fences; +} diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h index 2c4a7a00b..ec2899ffe 100644 --- a/lib/i915/gem_mman.h +++ b/lib/i915/gem_mman.h @@ -109,5 +109,11 @@ bool gem_has_mmap_offset_type(int fd, const struct mma= p_offset *t); (__t)++) \ for_each_if(gem_has_mmap_offset_type((fd), (__t))) +uint64_t gem_available_aperture_size(int fd); +uint64_t gem_aperture_size(int fd); +uint64_t gem_global_aperture_size(int fd); +uint64_t gem_mappable_aperture_size(int fd); +int gem_available_fences(int fd); + #endif /* GEM_MMAN_H */ diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c index 06431ce6c..a928f894f 100644 --- a/lib/ioctl_wrappers.c +++ b/lib/ioctl_wrappers.c @@ -782,31 +782,6 @@ bool gem_engine_reset_enabled(int fd) return gem_gpu_reset_type(fd) > 1; } -/** - * gem_available_fences: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the number of available fenc= es - * usable in a batchbuffer. Only relevant for pre-gen4. - * - * Returns: The number of available fences. - */ -int gem_available_fences(int fd) -{ - int num_fences; - struct drm_i915_getparam gp; - - memset(&gp, 0, sizeof(gp)); - gp.param =3D I915_PARAM_NUM_FENCES_AVAIL; - gp.value =3D &num_fences; - - num_fences =3D 0; - ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)); - errno =3D 0; - - return num_fences; -} - bool gem_has_llc(int fd) { int has_llc; @@ -929,97 +904,6 @@ uint64_t gem_total_stolen_size(int fd) return aperture.stolen_total_size; } -/** - * gem_available_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the available gpu aperture s= ize - * usable in a batchbuffer. - * - * Returns: The available gtt address space size. - */ -uint64_t gem_available_aperture_size(int fd) -{ - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - - return aperture.aper_available_size; -} - -/** - * gem_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the total gpu aperture size. - * - * Returns: The total gtt address space size. - */ -uint64_t gem_aperture_size(int fd) -{ - uint64_t aperture_size =3D 0; - struct drm_i915_gem_context_param p; - - memset(&p, 0, sizeof(p)); - p.param =3D 0x3; - if (__gem_context_get_param(fd, &p) =3D=3D 0) { - aperture_size =3D p.value; - } else { - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - aperture_size =3D aperture.aper_size; - } - - return aperture_size; -} - -/** - * gem_mappable_aperture_size: - * - * Feature test macro to query the kernel for the mappable gpu aperture si= ze. - * This is the area available for GTT memory mappings. - * - * Returns: The mappable gtt address space size. - */ -uint64_t gem_mappable_aperture_size(void) -{ - struct pci_device *pci_dev =3D intel_get_pci_device(); - int bar; - - if (intel_gen(pci_dev->device_id) < 3) - bar =3D 0; - else - bar =3D 2; - - return pci_dev->regions[bar].size; -} - -/** - * gem_global_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the global gpu aperture size= . - * This is the area available for the kernel to perform address translatio= ns. - * - * Returns: The gtt address space size. - */ -uint64_t gem_global_aperture_size(int fd) -{ - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - - return aperture.aper_size; -} - /** * gem_has_softpin: * @fd: open i915 drm file descriptor diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h index b76bea564..07879ae96 100644 --- a/lib/ioctl_wrappers.h +++ b/lib/ioctl_wrappers.h @@ -117,12 +117,7 @@ bool gem_uses_full_ppgtt(int fd); int gem_gpu_reset_type(int fd); bool gem_gpu_reset_enabled(int fd); bool gem_engine_reset_enabled(int fd); -int gem_available_fences(int fd); uint64_t gem_total_stolen_size(int fd); -uint64_t gem_available_aperture_size(int fd); -uint64_t gem_aperture_size(int fd); -uint64_t gem_global_aperture_size(int fd); -uint64_t gem_mappable_aperture_size(void); bool gem_has_softpin(int fd); bool gem_has_exec_fence(int fd); diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_al= l.c index 9ea94125e..da850a104 100644 --- a/tests/i915/gem_concurrent_all.c +++ b/tests/i915/gem_concurrent_all.c @@ -1828,7 +1828,7 @@ igt_main c->name, s->name, "small"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size()/4, + count =3D num_buffers(gem_mappable_= aperture_size(fd)/4, s, c, CHECK_RA= M); } run_modes(name, c, modes, s, count); @@ -1839,7 +1839,7 @@ igt_main c->name, s->name, "thrash"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M); } run_modes(name, c, modes, s, count); @@ -1871,7 +1871,7 @@ igt_main c->name, s->name, "shrink"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M); igt_fork_shrink_helper(fd); @@ -1887,8 +1887,8 @@ igt_main c->name, s->name, "swap"); igt_subtest_group { igt_fixture { - if (intel_get_avail_ram_mb() > gem_= mappable_aperture_size()/(1024*1024)) { - pin_sz =3D intel_get_avail_= ram_mb() - gem_mappable_aperture_size()/(1024*1024); + if (intel_get_avail_ram_mb() > gem_= mappable_aperture_size(fd)/(1024*1024)) { + pin_sz =3D intel_get_avail_= ram_mb() - gem_mappable_aperture_size(fd)/(1024*1024); igt_debug("Pinning %lld Mi= B\n", (long long)pin_sz); pin_sz *=3D 1024 * 1024; @@ -1902,7 +1902,7 @@ igt_main igt_require(pinned); } - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M | CHECK_SWAP); } run_modes(name, c, modes, s, count); diff --git a/tests/i915/gem_mmap.c b/tests/i915/gem_mmap.c index 8bad9b14e..60a64c134 100644 --- a/tests/i915/gem_mmap.c +++ b/tests/i915/gem_mmap.c @@ -53,10 +53,10 @@ test_huge_bo(int huge) switch (huge) { case -1: - huge_object_size =3D gem_mappable_aperture_size() / 2; + huge_object_size =3D gem_mappable_aperture_size(fd) / 2; break; case 0: - huge_object_size =3D gem_mappable_aperture_size() + PAGE_SI= ZE; + huge_object_size =3D gem_mappable_aperture_size(fd) + PAGE_= SIZE; break; case 1: huge_object_size =3D gem_aperture_size(fd) + PAGE_SIZE; diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c index 61fbc5bc7..528a7c726 100644 --- a/tests/i915/gem_mmap_gtt.c +++ b/tests/i915/gem_mmap_gtt.c @@ -905,7 +905,7 @@ test_huge_bo(int fd, int huge, int tiling) switch (huge) { case -1: - size =3D gem_mappable_aperture_size() / 2; + size =3D gem_mappable_aperture_size(fd) / 2; /* Power of two fence size, natural fence * alignment, and the guard page at the end @@ -920,7 +920,7 @@ test_huge_bo(int fd, int huge, int tiling) size /=3D 2; break; case 0: - size =3D gem_mappable_aperture_size() + PAGE_SIZE; + size =3D gem_mappable_aperture_size(fd) + PAGE_SIZE; break; default: size =3D gem_global_aperture_size(fd) + PAGE_SIZE; @@ -1001,13 +1001,13 @@ test_huge_copy(int fd, int huge, int tiling_a, int = tiling_b, int ncpus) switch (huge) { case -2: - huge_object_size =3D gem_mappable_aperture_size() / 4; + huge_object_size =3D gem_mappable_aperture_size(fd) / 4; break; case -1: - huge_object_size =3D gem_mappable_aperture_size() / 2; + huge_object_size =3D gem_mappable_aperture_size(fd) / 2; break; case 0: - huge_object_size =3D gem_mappable_aperture_size() + PAGE_SI= ZE; + huge_object_size =3D gem_mappable_aperture_size(fd) + PAGE_= SIZE; break; case 1: huge_object_size =3D gem_global_aperture_size(fd) + PAGE_S= IZE; diff --git a/tests/i915/gem_pwrite.c b/tests/i915/gem_pwrite.c index d2dcc95e8..f76d2bc70 100644 --- a/tests/i915/gem_pwrite.c +++ b/tests/i915/gem_pwrite.c @@ -130,7 +130,7 @@ static void test_big_cpu(int fd, int scale, unsigned fl= ags) switch (scale) { case 0: - size =3D gem_mappable_aperture_size() + 4096; + size =3D gem_mappable_aperture_size(fd) + 4096; break; case 1: size =3D gem_global_aperture_size(fd) + 4096; @@ -192,7 +192,7 @@ static void test_big_gtt(int fd, int scale, unsigned fl= ags) igt_require(gem_mmap__has_wc(fd)); switch (scale) { case 0: - size =3D gem_mappable_aperture_size() + 4096; + size =3D gem_mappable_aperture_size(fd) + 4096; break; case 1: size =3D gem_global_aperture_size(fd) + 4096; @@ -257,7 +257,7 @@ static void test_random(int fd) gem_require_mmap_wc(fd); size =3D min(intel_get_total_ram_mb() / 2, - gem_mappable_aperture_size() + 4096); + gem_mappable_aperture_size(fd) + 4096); intel_require_memory(1, size, CHECK_RAM); handle =3D gem_create(fd, size); diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c index dba62c8fa..023db8c56 100644 --- a/tests/i915/gem_shrink.c +++ b/tests/i915/gem_shrink.c @@ -439,7 +439,7 @@ igt_main * we expect the shrinker to start purging objects, * and possibly fail. */ - alloc_size =3D gem_mappable_aperture_size() / 2; + alloc_size =3D gem_mappable_aperture_size(fd) / 2; num_processes =3D 1 + (mem_size / (alloc_size >> 20)); igt_info("Using %d processes and %'lluMiB per process\n", diff --git a/tests/i915/gem_tiled_fence_blits.c b/tests/i915/gem_tiled_fenc= e_blits.c index 0a633d91b..28beea898 100644 --- a/tests/i915/gem_tiled_fence_blits.c +++ b/tests/i915/gem_tiled_fence_blits.c @@ -225,7 +225,7 @@ igt_main gem_require_blitter(fd); gem_require_mappable_ggtt(fd); - count =3D gem_mappable_aperture_size(); /* thrash fences! *= / + count =3D gem_mappable_aperture_size(fd); /* thrash fences!= */ if (count >> 32) count =3D MAX_32b; count =3D 3 + count / (1024 * 1024); diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c index 6d46c320c..6321dd403 100644 --- a/tests/i915/i915_pm_rpm.c +++ b/tests/i915/i915_pm_rpm.c @@ -1419,7 +1419,7 @@ static void gem_evict_pwrite_subtest(void) unsigned int num_trash_bos, n; uint32_t buf; - num_trash_bos =3D gem_mappable_aperture_size() / (1024*1024) + 1; + num_trash_bos =3D gem_mappable_aperture_size(drm_fd) / (1024*1024) = + 1; trash_bos =3D malloc(num_trash_bos * sizeof(*trash_bos)); igt_assert(trash_bos); @@ -1463,7 +1463,7 @@ static bool device_in_pci_d3(void) uint16_t val; int rc; - rc =3D pci_device_cfg_read_u16(intel_get_pci_device(), &val, 0xd4); + rc =3D pci_device_cfg_read_u16(igt_device_get_pci_device(drm_fd), &= val, 0xd4); igt_assert_eq(rc, 0); igt_debug("%s: PCI D3 state=3D%d\n", __func__, val & 0x3); diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c index 02e9915ba..8794ace08 100644 --- a/tests/kms_big_fb.c +++ b/tests/kms_big_fb.c @@ -645,7 +645,7 @@ igt_main data.ram_size =3D intel_get_total_ram_mb() << 20; data.aper_size =3D gem_aperture_size(data.drm_fd); - data.mappable_size =3D gem_mappable_aperture_size(); + data.mappable_size =3D gem_mappable_aperture_size(data.drm_= fd); igt_info("RAM: %"PRIu64" MiB, GPU address space: %"PRId64"= MiB, GGTT mappable size: %"PRId64" MiB\n", data.ram_size >> 20, data.aper_size >> 20, diff --git a/tests/kms_flip.c b/tests/kms_flip.c index 51b9ac950..0f0565cf6 100755 --- a/tests/kms_flip.c +++ b/tests/kms_flip.c @@ -1282,7 +1282,7 @@ static void __run_test_on_crtc_set(struct test_output= *o, int *crtc_idxs, /* 256 MB is usually the maximum mappable aperture, * (make it 4x times that to ensure failure) */ if (o->flags & TEST_BO_TOOBIG) { - bo_size =3D 4*gem_mappable_aperture_size(); + bo_size =3D 4*gem_mappable_aperture_size(drm_fd); igt_require(bo_size < gem_global_aperture_size(drm_fd)); } diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c index 143342410..7c43ced85 100644 --- a/tests/prime_mmap.c +++ b/tests/prime_mmap.c @@ -447,8 +447,8 @@ test_aperture_limit(void) char *ptr1, *ptr2; uint32_t handle1, handle2; /* Two buffers the sum of which > mappable aperture */ - uint64_t size1 =3D (gem_mappable_aperture_size() * 7) / 8; - uint64_t size2 =3D (gem_mappable_aperture_size() * 3) / 8; + uint64_t size1 =3D (gem_mappable_aperture_size(fd) * 7) / 8; + uint64_t size2 =3D (gem_mappable_aperture_size(fd) * 3) / 8; handle1 =3D gem_create(fd, size1); fill_bo(handle1, BO_SIZE); -- 2.29.2 --_000_7021dc5149a24438878f6540a0c4aed8intelcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Some minor comments as below.


Reviewed-by: Bruce Chang <yu.bruce.chang@intel.com>

From: Chris Wilson <ch= ris@chris-wilson.co.uk>
Sent: Saturday, December 12, 2020 1:43 AM
To: intel-gfx@lists.freedesktop.org
Cc: igt-dev@lists.freedesktop.org; Chris Wilson; Chang, Yu bruce
Subject: [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture= _size()
 
In order to find the co= rrect aperture size for the test, we want to pass
the test's device into the query.

Reported-by: Bruce Chang <yu.bruce.chang@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bruce Chang <yu.bruce.chang@intel.com>
---
 lib/i915/gem_mman.c        &n= bsp;       | 108 +++++= 3;++++++++++++++= 3;++++++
 lib/i915/gem_mman.h        &n= bsp;       |   6 ++
 lib/ioctl_wrappers.c        &= nbsp;      | 116 -----------------------------
 lib/ioctl_wrappers.h        &= nbsp;      |   5 --
 tests/i915/gem_concurrent_all.c    |  12 +--<= br>  tests/i915/gem_mmap.c        =       |   4 +-
 tests/i915/gem_mmap_gtt.c       &n= bsp;  |  10 +--
 tests/i915/gem_pwrite.c       &nbs= p;    |   6 +-
 tests/i915/gem_shrink.c       &nbs= p;    |   2 +-
 tests/i915/gem_tiled_fence_blits.c |   2 +-
 tests/i915/i915_pm_rpm.c       &nb= sp;   |   4 +-
 tests/kms_big_fb.c        &nb= sp;        |   2 +-
 tests/kms_flip.c         = ;          |   2 = 3;-
 tests/prime_mmap.c        &nb= sp;        |   4 +-
 14 files changed, 138 insertions(+), 145 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 93bef2bfc..703c6a5c1 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -27,7 +27,9 @@
 #include <errno.h>
 
 #include "igt_core.h"
+#include "igt_device.h"
 #include "ioctl_wrappers.h"
+#include "intel_chipset.h"
 
 #include "gem_mman.h"
 
@@ -551,3 +553,109 @@ const struct mmap_offset mmap_offset_types[] =3D = {
         { "uc", I915_MMA= P_OFFSET_UC, I915_GEM_DOMAIN_WC },
         {},
 };
+
+/**
+ * gem_available_aperture_size:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query the kernel for the available gpu apertu= re size
+ * usable in a batchbuffer.
+ *
+ * Returns: The available gtt address space size.
+ */
+uint64_t gem_available_aperture_size(int fd)
+{
+       struct drm_i915_gem_get_aperture = aperture =3D {
+           &nbs= p;   aperture.aper_available_size =3D 256*1024*1024,
+       };
+
+       ioctl(fd, DRM_IOCTL_I915_GEM_GET_= APERTURE, &aperture);
+       errno =3D 0;
+
+       return aperture.aper_available_si= ze;
+}
+
+/**
+ * gem_aperture_size:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query the kernel for the total gpu aperture s= ize.
+ *
+ * Returns: The total gtt address space size.
+ */
+uint64_t gem_aperture_size(int fd)
+{
+       struct drm_i915_gem_context_param= p =3D {
+           &nbs= p;   .param =3D 0x3
+       };

Understand this is the = original code, but it will be more readable to use I915_CONTEXT_= PARAM_GTT_SIZE instead of 3.

+
+       if (__gem_context_get_param(fd, &= amp;p))
+           &nbs= p;   p.value =3D gem_global_aperture_size(fd);
+
+       return p.value;
+}
+
+/**
+ * gem_mappable_aperture_size:
+ *
+ * Feature test macro to query the kernel for the mappable gpu apertur= e size.
+ * This is the area available for GTT memory mappings.
+ *
+ * Returns: The mappable gtt address space size.
+ */
+uint64_t gem_mappable_aperture_size(int fd)
+{
+       struct pci_device *pci_dev =3D ig= t_device_get_pci_device(fd);

Does it m= ake sense to eliminate the function intel_get_pci_device() if not being u= sed anymore? But it can be a separate patch.
<= br> +     =   int bar;
+
+       = if (intel_gen(pci_dev->device_id) < 3)
+      &= nbsp;        bar =3D 0;
+       = else
+      &= nbsp;        bar =3D 2;
+
+       = return pci_dev->regions[bar].size;
+}
+
+/**
+ * gem_global_aperture_size: + * @fd: open i915 drm file descriptor=
+ *
+ * Feature test macro to query the ke= rnel for the global gpu aperture size.
+ * This is the area available for the= kernel to perform address translations.
+ *
+ * Returns: The gtt address space siz= e.
+ */
+uint64_t gem_global_aperture_size(int= fd)
+{
+       = struct drm_i915_gem_get_aperture aperture =3D {
+      &= nbsp;        aperture.aper_size =3D 256*= 1024*1024
+       = };
+
+       = ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+       = errno =3D 0;
+
+       = return aperture.aper_size;
+}
+
+/**
+ * gem_available_fences:
+ * @fd: open i915 drm file descriptor=
+ *
+ * Feature test macro to query the ke= rnel for the number of available fences
+ * usable in a batchbuffer. Only rele= vant for pre-gen4.
+ *
+ * Returns: The number of available f= ences.
+ */
+int gem_available_fences(int fd)
+{
+       = int num_fences =3D 0;
+       = struct drm_i915_getparam gp =3D {
+      &= nbsp;        gp.param =3D I915_PARAM_NUM= _FENCES_AVAIL,
+      &= nbsp;        gp.value =3D &num_fence= s,
+       = };
+
+       = ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
+       = errno =3D 0;
+
+       = return num_fences;
+}
diff --git a/lib/i915/gem_mman.h b/lib/i91= 5/gem_mman.h
index 2c4a7a00b..ec2899ffe 100644 --- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -109,5 +109,11 @@ bool gem_has_mmap= _offset_type(int fd, const struct mmap_offset *t);
       =        (__t)++) \
       =           for_each_if(gem_has_= mmap_offset_type((fd), (__t)))
 
+uint64_t gem_available_aperture_size(= int fd);
+uint64_t gem_aperture_size(int fd);
+uint64_t gem_global_aperture_size(int= fd);
+uint64_t gem_mappable_aperture_size(i= nt fd);
+int gem_available_fences(int fd);
+
 #endif /* GEM_MMAN_H */
 
diff --git a/lib/ioctl_wrappers.c b/lib/io= ctl_wrappers.c
index 06431ce6c..a928f894f 100644 --- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -782,31 +782,6 @@ bool gem_engine_r= eset_enabled(int fd)
       =   return gem_gpu_reset_type(fd) > 1;
 }
 
-/**
- * gem_available_fences:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the number of available fences
- * usable in a batchbuffer. Only relevant= for pre-gen4.
- *
- * Returns: The number of available fence= s.
- */
-int gem_available_fences(int fd) -{
-       int = num_fences;
-       stru= ct drm_i915_getparam gp;
-
-       mems= et(&gp, 0, sizeof(gp));
-       gp.p= aram =3D I915_PARAM_NUM_FENCES_AVAIL;
-       gp.v= alue =3D &num_fences;
-
-       num_= fences =3D 0;
-       ioct= l(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
-       errn= o =3D 0;
-
-       retu= rn num_fences;
-}
-
 bool gem_has_llc(int fd)
 {
       =   int has_llc;
@@ -929,97 +904,6 @@ uint64_t gem_tota= l_stolen_size(int fd)
       =   return aperture.stolen_total_size;
 }
 
-/**
- * gem_available_aperture_size: - * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the available gpu aperture size
- * usable in a batchbuffer.
- *
- * Returns: The available gtt address spa= ce size.
- */
-uint64_t gem_available_aperture_size(int = fd)
-{
-       stru= ct drm_i915_gem_get_aperture aperture;
-
-       mems= et(&aperture, 0, sizeof(aperture));
-       aper= ture.aper_size =3D 256*1024*1024;
-       do_i= octl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
-
-       retu= rn aperture.aper_available_size;
-}
-
-/**
- * gem_aperture_size:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the total gpu aperture size.
- *
- * Returns: The total gtt address space s= ize.
- */
-uint64_t gem_aperture_size(int fd)=
-{
-       uint= 64_t aperture_size =3D 0;
-       stru= ct drm_i915_gem_context_param p;
-
-       mems= et(&p, 0, sizeof(p));
-       p.pa= ram =3D 0x3;
-       if (= __gem_context_get_param(fd, &p) =3D=3D 0) {
-       = ;        aperture_size =3D p.value;
-       } el= se {
-       = ;        struct drm_i915_gem_get_apertur= e aperture;
-
-       = ;        memset(&aperture, 0, sizeof= (aperture));
-       = ;        aperture.aper_size =3D 256*1024= *1024;
-
-       = ;        do_ioctl(fd, DRM_IOCTL_I915_GEM= _GET_APERTURE, &aperture);
-       = ;        aperture_size =3D  apertur= e.aper_size;
-       }
-
-       retu= rn aperture_size;
-}
-
-/**
- * gem_mappable_aperture_size:
- *
- * Feature test macro to query the kernel= for the mappable gpu aperture size.
- * This is the area available for GTT mem= ory mappings.
- *
- * Returns: The mappable gtt address spac= e size.
- */
-uint64_t gem_mappable_aperture_size(void)=
-{
-       stru= ct pci_device *pci_dev =3D intel_get_pci_device();
-       int = bar;
-
-       if (= intel_gen(pci_dev->device_id) < 3)
-       = ;        bar =3D 0;
-       else=
-       = ;        bar =3D 2;
-
-       retu= rn pci_dev->regions[bar].size;
-}
-
-/**
- * gem_global_aperture_size:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the global gpu aperture size.
- * This is the area available for the ker= nel to perform address translations.
- *
- * Returns: The gtt address space size.
- */
-uint64_t gem_global_aperture_size(int fd)=
-{
-       stru= ct drm_i915_gem_get_aperture aperture;
-
-       mems= et(&aperture, 0, sizeof(aperture));
-       aper= ture.aper_size =3D 256*1024*1024;
-       do_i= octl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
-
-       retu= rn aperture.aper_size;
-}
-
 /**
  * gem_has_softpin:
  * @fd: open i915 drm file descripto= r
diff --git a/lib/ioctl_wrappers.h b/lib/io= ctl_wrappers.h
index b76bea564..07879ae96 100644 --- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -117,12 +117,7 @@ bool gem_uses_ful= l_ppgtt(int fd);
 int gem_gpu_reset_type(int fd);
 bool gem_gpu_reset_enabled(int fd);<= /span>
 bool gem_engine_reset_enabled(int fd= );
-int gem_available_fences(int fd);<= br>  uint64_t gem_total_stolen_size(int f= d);
-uint64_t gem_available_aperture_size(int = fd);
-uint64_t gem_aperture_size(int fd);
-uint64_t gem_global_aperture_size(int fd)= ;
-uint64_t gem_mappable_aperture_size(void)= ;
 bool gem_has_softpin(int fd);=
 bool gem_has_exec_fence(int fd);
 
diff --git a/tests/i915/gem_concurrent_all= .c b/tests/i915/gem_concurrent_all.c
index 9ea94125e..da850a104 100644 --- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurren= t_all.c
@@ -1828,7 +1828,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "small");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size()/4,
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd)/4,
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
@@ -1839,7 +1839,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "thrash");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
@@ -1871,7 +1871,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "shrink");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
 
       =             &nb= sp;            =          igt_fork_shrink_helper(fd)= ;
@@ -1887,8 +1887,8 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "swap");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       if (intel_get_avail_ram_mb() > gem= _mappable_aperture_size()/(1024*1024)) {
-       = ;            &n= bsp;            = ;            &n= bsp;  pin_sz =3D intel_get_avail_ram_mb() - gem_mappable_aperture_size= ()/(1024*1024);
+      &= nbsp;           &nbs= p;            &= nbsp;       if (intel_get_avail_ram_mb() >= gem_mappable_aperture_size(fd)/(1024*1024)) {
+      &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;   pin_sz =3D intel_get_avail_ram_mb() - gem_mappable_aperture_= size(fd)/(1024*1024);
 
       =             &nb= sp;            =             &nb= sp;    igt_debug("Pinning %lld MiB\n", (long long)= pin_sz);
       =             &nb= sp;            =             &nb= sp;    pin_sz *=3D 1024 * 1024;
@@ -1902,7 +1902,7 @@ igt_main<= br>        =             &nb= sp;            =             &nb= sp;    igt_require(pinned);
       =             &nb= sp;            =          }
 
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM | CHECK_SWAP);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
diff --git a/tests/i915/gem_mmap.c b/tests= /i915/gem_mmap.c
index 8bad9b14e..60a64c134 100644 --- a/tests/i915/gem_mmap.c
+++ b/tests/i915/gem_mmap.c
@@ -53,10 +53,10 @@ test_huge_bo(int h= uge)
 
       =   switch (huge) {
       =   case -1:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 2;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 2;
       =           break;
       =   case 0:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() + PAGE_SIZE;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) + PAGE_SIZE;
       =           break;
       =   case 1:
       =           huge_object_size =3D= gem_aperture_size(fd) + PAGE_SIZE;
diff --git a/tests/i915/gem_mmap_gtt.c b/t= ests/i915/gem_mmap_gtt.c
index 61fbc5bc7..528a7c726 100644 --- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.= c
@@ -905,7 +905,7 @@ test_huge_bo(int f= d, int huge, int tiling)
 
       =   switch (huge) {
       =   case -1:
-       = ;        size =3D gem_mappable_aperture_= size() / 2;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) / 2;
 
       =           /* Power of two fenc= e size, natural fence
       =            * alignment, a= nd the guard page at the end
@@ -920,7 +920,7 @@ test_huge_bo(int f= d, int huge, int tiling)
       =             &nb= sp;     size /=3D 2;
       =           break;
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + PAGE_SIZE;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + PAGE_SIZE;
       =           break;
       =   default:
       =           size =3D gem_global_= aperture_size(fd) + PAGE_SIZE;
@@ -1001,13 +1001,13 @@ test_huge_copy= (int fd, int huge, int tiling_a, int tiling_b, int ncpus)
 
       =   switch (huge) {
       =   case -2:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 4;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 4;
       =           break;
       =   case -1:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 2;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 2;
       =           break;
       =   case 0:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() + PAGE_SIZE;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) + PAGE_SIZE;
       =           break;
       =   case 1:
       =           huge_object_size =3D= gem_global_aperture_size(fd) + PAGE_SIZE;
diff --git a/tests/i915/gem_pwrite.c b/tes= ts/i915/gem_pwrite.c
index d2dcc95e8..f76d2bc70 100644 --- a/tests/i915/gem_pwrite.c
+++ b/tests/i915/gem_pwrite.c<= /span>
@@ -130,7 +130,7 @@ static void test_b= ig_cpu(int fd, int scale, unsigned flags)
 
       =   switch (scale) {
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + 4096;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + 4096;
       =           break;
       =   case 1:
       =           size =3D gem_global_= aperture_size(fd) + 4096;
@@ -192,7 +192,7 @@ static void test_b= ig_gtt(int fd, int scale, unsigned flags)
       =   igt_require(gem_mmap__has_wc(fd));
       =   switch (scale) {
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + 4096;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + 4096;
       =           break;
       =   case 1:
       =           size =3D gem_global_= aperture_size(fd) + 4096;
@@ -257,7 +257,7 @@ static void test_r= andom(int fd)
       =   gem_require_mmap_wc(fd);
 
       =   size =3D min(intel_get_total_ram_mb() / 2,
-       = ;            gem_map= pable_aperture_size() + 4096);
+      &= nbsp;            gem= _mappable_aperture_size(fd) + 4096);
       =   intel_require_memory(1, size, CHECK_RAM);
 
       =   handle =3D gem_create(fd, size);
diff --git a/tests/i915/gem_shrink.c b/tes= ts/i915/gem_shrink.c
index dba62c8fa..023db8c56 100644 --- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c<= /span>
@@ -439,7 +439,7 @@ igt_main        =            * we expect th= e shrinker to start purging objects,
       =            * and possibly= fail.
       =            */
-       = ;        alloc_size =3D gem_mappable_ape= rture_size() / 2;
+      &= nbsp;        alloc_size =3D gem_mappable= _aperture_size(fd) / 2;
       =           num_processes =3D 1 = + (mem_size / (alloc_size >> 20));
 
       =           igt_info("Using= %d processes and %'lluMiB per process\n",
diff --git a/tests/i915/gem_tiled_fence_bl= its.c b/tests/i915/gem_tiled_fence_blits.c
index 0a633d91b..28beea898 100644 --- a/tests/i915/gem_tiled_fence_blits.c
+++ b/tests/i915/gem_tiled_fen= ce_blits.c
@@ -225,7 +225,7 @@ igt_main        =           gem_require_blitter(= fd);
       =           gem_require_mappable= _ggtt(fd);
 
-       = ;        count =3D gem_mappable_aperture= _size(); /* thrash fences! */
+      &= nbsp;        count =3D gem_mappable_aper= ture_size(fd); /* thrash fences! */
       =           if (count >> 3= 2)
       =             &nb= sp;     count =3D MAX_32b;
       =           count =3D 3 + co= unt / (1024 * 1024);
diff --git a/tests/i915/i915_pm_rpm.c b/te= sts/i915/i915_pm_rpm.c
index 6d46c320c..6321dd403 100644 --- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c=
@@ -1419,7 +1419,7 @@ static void gem_= evict_pwrite_subtest(void)
       =   unsigned int num_trash_bos, n;
       =   uint32_t buf;
 
-       num_= trash_bos =3D gem_mappable_aperture_size() / (1024*1024) + 1; +       = num_trash_bos =3D gem_mappable_aperture_size(drm_fd) / (1024*1024) + 1;=
       =   trash_bos =3D malloc(num_trash_bos * sizeof(*trash_bos));
       =   igt_assert(trash_bos);
 
@@ -1463,7 +1463,7 @@ static bool devi= ce_in_pci_d3(void)
       =   uint16_t val;
       =   int rc;
 
-       rc = =3D pci_device_cfg_read_u16(intel_get_pci_device(), &val, 0xd4);=
+       = rc =3D pci_device_cfg_read_u16(igt_device_get_pci_device(drm_fd), &val,= 0xd4);
       =   igt_assert_eq(rc, 0);
 
       =   igt_debug("%s: PCI D3 state=3D%d\n", __func__, val & 0= x3);
diff --git a/tests/kms_big_fb.c b/tests/km= s_big_fb.c
index 02e9915ba..8794ace08 100644 --- a/tests/kms_big_fb.c
+++ b/tests/kms_big_fb.c
@@ -645,7 +645,7 @@ igt_main  
       =           data.ram_size =3D in= tel_get_total_ram_mb() << 20;
       =           data.aper_size =3D g= em_aperture_size(data.drm_fd);
-       = ;        data.mappable_size =3D gem_mapp= able_aperture_size();
+      &= nbsp;        data.mappable_size =3D gem_= mappable_aperture_size(data.drm_fd);
 
       =           igt_info("RAM: = %"PRIu64" MiB, GPU address space: %"PRId64" MiB, GGTT m= appable size: %"PRId64" MiB\n",
       =             &nb= sp;      data.ram_size >> 20, data.aper_size= >> 20,
diff --git a/tests/kms_flip.c b/tests/kms_= flip.c
index 51b9ac950..0f0565cf6 100755 --- a/tests/kms_flip.c
+++ b/tests/kms_flip.c<= br> @@ -1282,7 +1282,7 @@ static void __ru= n_test_on_crtc_set(struct test_output *o, int *crtc_idxs,
       =   /* 256 MB is usually the maximum mappable aperture,
       =    * (make it 4x times that to ensure failure) */
       =   if (o->flags & TEST_BO_TOOBIG) {
-       = ;        bo_size =3D 4*gem_mappable_aper= ture_size();
+      &= nbsp;        bo_size =3D 4*gem_mappable_= aperture_size(drm_fd);
       =           igt_require(bo_size = < gem_global_aperture_size(drm_fd));
       =   }
 
diff --git a/tests/prime_mmap.c b/tests/pr= ime_mmap.c
index 143342410..7c43ced85 100644 --- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -447,8 +447,8 @@ test_aperture_limi= t(void)
       =   char *ptr1, *ptr2;
       =   uint32_t handle1, handle2;
       =   /* Two buffers the sum of which > mappable aperture */
-       uint= 64_t size1 =3D (gem_mappable_aperture_size() * 7) / 8;
-       uint= 64_t size2 =3D (gem_mappable_aperture_size() * 3) / 8;
+       = uint64_t size1 =3D (gem_mappable_aperture_size(fd) * 7) / 8;
+       = uint64_t size2 =3D (gem_mappable_aperture_size(fd) * 3) / 8;
 
       =   handle1 =3D gem_create(fd, size1);
       =   fill_bo(handle1, BO_SIZE);
--
2.29.2

--_000_7021dc5149a24438878f6540a0c4aed8intelcom_-- --===============1014413096== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1014413096==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: "Chang, Yu bruce" Date: Mon, 14 Dec 2020 18:45:04 +0000 Message-ID: <7021dc5149a24438878f6540a0c4aed8@intel.com> References: <20201212094354.3023502-1-chris@chris-wilson.co.uk> In-Reply-To: <20201212094354.3023502-1-chris@chris-wilson.co.uk> Content-Language: en-US MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture_size() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1820657663==" Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To: Chris Wilson , "intel-gfx@lists.freedesktop.org" Cc: "igt-dev@lists.freedesktop.org" List-ID: --===============1820657663== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_7021dc5149a24438878f6540a0c4aed8intelcom_" --_000_7021dc5149a24438878f6540a0c4aed8intelcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Some minor comments as below. Reviewed-by: Bruce Chang ________________________________ From: Chris Wilson Sent: Saturday, December 12, 2020 1:43 AM To: intel-gfx@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org; Chris Wilson; Chang, Yu bruce Subject: [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture_size() In order to find the correct aperture size for the test, we want to pass the test's device into the query. Reported-by: Bruce Chang Signed-off-by: Chris Wilson Cc: Bruce Chang --- lib/i915/gem_mman.c | 108 +++++++++++++++++++++++++++ lib/i915/gem_mman.h | 6 ++ lib/ioctl_wrappers.c | 116 ----------------------------- lib/ioctl_wrappers.h | 5 -- tests/i915/gem_concurrent_all.c | 12 +-- tests/i915/gem_mmap.c | 4 +- tests/i915/gem_mmap_gtt.c | 10 +-- tests/i915/gem_pwrite.c | 6 +- tests/i915/gem_shrink.c | 2 +- tests/i915/gem_tiled_fence_blits.c | 2 +- tests/i915/i915_pm_rpm.c | 4 +- tests/kms_big_fb.c | 2 +- tests/kms_flip.c | 2 +- tests/prime_mmap.c | 4 +- 14 files changed, 138 insertions(+), 145 deletions(-) diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c index 93bef2bfc..703c6a5c1 100644 --- a/lib/i915/gem_mman.c +++ b/lib/i915/gem_mman.c @@ -27,7 +27,9 @@ #include #include "igt_core.h" +#include "igt_device.h" #include "ioctl_wrappers.h" +#include "intel_chipset.h" #include "gem_mman.h" @@ -551,3 +553,109 @@ const struct mmap_offset mmap_offset_types[] =3D { { "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC }, {}, }; + +/** + * gem_available_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the available gpu aperture s= ize + * usable in a batchbuffer. + * + * Returns: The available gtt address space size. + */ +uint64_t gem_available_aperture_size(int fd) +{ + struct drm_i915_gem_get_aperture aperture =3D { + aperture.aper_available_size =3D 256*1024*1024, + }; + + ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + errno =3D 0; + + return aperture.aper_available_size; +} + +/** + * gem_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the total gpu aperture size. + * + * Returns: The total gtt address space size. + */ +uint64_t gem_aperture_size(int fd) +{ + struct drm_i915_gem_context_param p =3D { + .param =3D 0x3 + }; Understand this is the original code, but it will be more readable to use I= 915_CONTEXT_PARAM_GTT_SIZE instead of 3. + + if (__gem_context_get_param(fd, &p)) + p.value =3D gem_global_aperture_size(fd); + + return p.value; +} + +/** + * gem_mappable_aperture_size: + * + * Feature test macro to query the kernel for the mappable gpu aperture si= ze. + * This is the area available for GTT memory mappings. + * + * Returns: The mappable gtt address space size. + */ +uint64_t gem_mappable_aperture_size(int fd) +{ + struct pci_device *pci_dev =3D igt_device_get_pci_device(fd); Does it make sense to eliminate the function intel_get_pci_device() if not = being used anymore? But it can be a separate patch. + int bar; + + if (intel_gen(pci_dev->device_id) < 3) + bar =3D 0; + else + bar =3D 2; + + return pci_dev->regions[bar].size; +} + +/** + * gem_global_aperture_size: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the global gpu aperture size= . + * This is the area available for the kernel to perform address translatio= ns. + * + * Returns: The gtt address space size. + */ +uint64_t gem_global_aperture_size(int fd) +{ + struct drm_i915_gem_get_aperture aperture =3D { + aperture.aper_size =3D 256*1024*1024 + }; + + ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + errno =3D 0; + + return aperture.aper_size; +} + +/** + * gem_available_fences: + * @fd: open i915 drm file descriptor + * + * Feature test macro to query the kernel for the number of available fenc= es + * usable in a batchbuffer. Only relevant for pre-gen4. + * + * Returns: The number of available fences. + */ +int gem_available_fences(int fd) +{ + int num_fences =3D 0; + struct drm_i915_getparam gp =3D { + gp.param =3D I915_PARAM_NUM_FENCES_AVAIL, + gp.value =3D &num_fences, + }; + + ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)); + errno =3D 0; + + return num_fences; +} diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h index 2c4a7a00b..ec2899ffe 100644 --- a/lib/i915/gem_mman.h +++ b/lib/i915/gem_mman.h @@ -109,5 +109,11 @@ bool gem_has_mmap_offset_type(int fd, const struct mma= p_offset *t); (__t)++) \ for_each_if(gem_has_mmap_offset_type((fd), (__t))) +uint64_t gem_available_aperture_size(int fd); +uint64_t gem_aperture_size(int fd); +uint64_t gem_global_aperture_size(int fd); +uint64_t gem_mappable_aperture_size(int fd); +int gem_available_fences(int fd); + #endif /* GEM_MMAN_H */ diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c index 06431ce6c..a928f894f 100644 --- a/lib/ioctl_wrappers.c +++ b/lib/ioctl_wrappers.c @@ -782,31 +782,6 @@ bool gem_engine_reset_enabled(int fd) return gem_gpu_reset_type(fd) > 1; } -/** - * gem_available_fences: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the number of available fenc= es - * usable in a batchbuffer. Only relevant for pre-gen4. - * - * Returns: The number of available fences. - */ -int gem_available_fences(int fd) -{ - int num_fences; - struct drm_i915_getparam gp; - - memset(&gp, 0, sizeof(gp)); - gp.param =3D I915_PARAM_NUM_FENCES_AVAIL; - gp.value =3D &num_fences; - - num_fences =3D 0; - ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)); - errno =3D 0; - - return num_fences; -} - bool gem_has_llc(int fd) { int has_llc; @@ -929,97 +904,6 @@ uint64_t gem_total_stolen_size(int fd) return aperture.stolen_total_size; } -/** - * gem_available_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the available gpu aperture s= ize - * usable in a batchbuffer. - * - * Returns: The available gtt address space size. - */ -uint64_t gem_available_aperture_size(int fd) -{ - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - - return aperture.aper_available_size; -} - -/** - * gem_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the total gpu aperture size. - * - * Returns: The total gtt address space size. - */ -uint64_t gem_aperture_size(int fd) -{ - uint64_t aperture_size =3D 0; - struct drm_i915_gem_context_param p; - - memset(&p, 0, sizeof(p)); - p.param =3D 0x3; - if (__gem_context_get_param(fd, &p) =3D=3D 0) { - aperture_size =3D p.value; - } else { - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - aperture_size =3D aperture.aper_size; - } - - return aperture_size; -} - -/** - * gem_mappable_aperture_size: - * - * Feature test macro to query the kernel for the mappable gpu aperture si= ze. - * This is the area available for GTT memory mappings. - * - * Returns: The mappable gtt address space size. - */ -uint64_t gem_mappable_aperture_size(void) -{ - struct pci_device *pci_dev =3D intel_get_pci_device(); - int bar; - - if (intel_gen(pci_dev->device_id) < 3) - bar =3D 0; - else - bar =3D 2; - - return pci_dev->regions[bar].size; -} - -/** - * gem_global_aperture_size: - * @fd: open i915 drm file descriptor - * - * Feature test macro to query the kernel for the global gpu aperture size= . - * This is the area available for the kernel to perform address translatio= ns. - * - * Returns: The gtt address space size. - */ -uint64_t gem_global_aperture_size(int fd) -{ - struct drm_i915_gem_get_aperture aperture; - - memset(&aperture, 0, sizeof(aperture)); - aperture.aper_size =3D 256*1024*1024; - do_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); - - return aperture.aper_size; -} - /** * gem_has_softpin: * @fd: open i915 drm file descriptor diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h index b76bea564..07879ae96 100644 --- a/lib/ioctl_wrappers.h +++ b/lib/ioctl_wrappers.h @@ -117,12 +117,7 @@ bool gem_uses_full_ppgtt(int fd); int gem_gpu_reset_type(int fd); bool gem_gpu_reset_enabled(int fd); bool gem_engine_reset_enabled(int fd); -int gem_available_fences(int fd); uint64_t gem_total_stolen_size(int fd); -uint64_t gem_available_aperture_size(int fd); -uint64_t gem_aperture_size(int fd); -uint64_t gem_global_aperture_size(int fd); -uint64_t gem_mappable_aperture_size(void); bool gem_has_softpin(int fd); bool gem_has_exec_fence(int fd); diff --git a/tests/i915/gem_concurrent_all.c b/tests/i915/gem_concurrent_al= l.c index 9ea94125e..da850a104 100644 --- a/tests/i915/gem_concurrent_all.c +++ b/tests/i915/gem_concurrent_all.c @@ -1828,7 +1828,7 @@ igt_main c->name, s->name, "small"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size()/4, + count =3D num_buffers(gem_mappable_= aperture_size(fd)/4, s, c, CHECK_RA= M); } run_modes(name, c, modes, s, count); @@ -1839,7 +1839,7 @@ igt_main c->name, s->name, "thrash"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M); } run_modes(name, c, modes, s, count); @@ -1871,7 +1871,7 @@ igt_main c->name, s->name, "shrink"); igt_subtest_group { igt_fixture { - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M); igt_fork_shrink_helper(fd); @@ -1887,8 +1887,8 @@ igt_main c->name, s->name, "swap"); igt_subtest_group { igt_fixture { - if (intel_get_avail_ram_mb() > gem_= mappable_aperture_size()/(1024*1024)) { - pin_sz =3D intel_get_avail_= ram_mb() - gem_mappable_aperture_size()/(1024*1024); + if (intel_get_avail_ram_mb() > gem_= mappable_aperture_size(fd)/(1024*1024)) { + pin_sz =3D intel_get_avail_= ram_mb() - gem_mappable_aperture_size(fd)/(1024*1024); igt_debug("Pinning %lld Mi= B\n", (long long)pin_sz); pin_sz *=3D 1024 * 1024; @@ -1902,7 +1902,7 @@ igt_main igt_require(pinned); } - count =3D num_buffers(gem_mappable_= aperture_size(), + count =3D num_buffers(gem_mappable_= aperture_size(fd), s, c, CHECK_RA= M | CHECK_SWAP); } run_modes(name, c, modes, s, count); diff --git a/tests/i915/gem_mmap.c b/tests/i915/gem_mmap.c index 8bad9b14e..60a64c134 100644 --- a/tests/i915/gem_mmap.c +++ b/tests/i915/gem_mmap.c @@ -53,10 +53,10 @@ test_huge_bo(int huge) switch (huge) { case -1: - huge_object_size =3D gem_mappable_aperture_size() / 2; + huge_object_size =3D gem_mappable_aperture_size(fd) / 2; break; case 0: - huge_object_size =3D gem_mappable_aperture_size() + PAGE_SI= ZE; + huge_object_size =3D gem_mappable_aperture_size(fd) + PAGE_= SIZE; break; case 1: huge_object_size =3D gem_aperture_size(fd) + PAGE_SIZE; diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_gtt.c index 61fbc5bc7..528a7c726 100644 --- a/tests/i915/gem_mmap_gtt.c +++ b/tests/i915/gem_mmap_gtt.c @@ -905,7 +905,7 @@ test_huge_bo(int fd, int huge, int tiling) switch (huge) { case -1: - size =3D gem_mappable_aperture_size() / 2; + size =3D gem_mappable_aperture_size(fd) / 2; /* Power of two fence size, natural fence * alignment, and the guard page at the end @@ -920,7 +920,7 @@ test_huge_bo(int fd, int huge, int tiling) size /=3D 2; break; case 0: - size =3D gem_mappable_aperture_size() + PAGE_SIZE; + size =3D gem_mappable_aperture_size(fd) + PAGE_SIZE; break; default: size =3D gem_global_aperture_size(fd) + PAGE_SIZE; @@ -1001,13 +1001,13 @@ test_huge_copy(int fd, int huge, int tiling_a, int = tiling_b, int ncpus) switch (huge) { case -2: - huge_object_size =3D gem_mappable_aperture_size() / 4; + huge_object_size =3D gem_mappable_aperture_size(fd) / 4; break; case -1: - huge_object_size =3D gem_mappable_aperture_size() / 2; + huge_object_size =3D gem_mappable_aperture_size(fd) / 2; break; case 0: - huge_object_size =3D gem_mappable_aperture_size() + PAGE_SI= ZE; + huge_object_size =3D gem_mappable_aperture_size(fd) + PAGE_= SIZE; break; case 1: huge_object_size =3D gem_global_aperture_size(fd) + PAGE_S= IZE; diff --git a/tests/i915/gem_pwrite.c b/tests/i915/gem_pwrite.c index d2dcc95e8..f76d2bc70 100644 --- a/tests/i915/gem_pwrite.c +++ b/tests/i915/gem_pwrite.c @@ -130,7 +130,7 @@ static void test_big_cpu(int fd, int scale, unsigned fl= ags) switch (scale) { case 0: - size =3D gem_mappable_aperture_size() + 4096; + size =3D gem_mappable_aperture_size(fd) + 4096; break; case 1: size =3D gem_global_aperture_size(fd) + 4096; @@ -192,7 +192,7 @@ static void test_big_gtt(int fd, int scale, unsigned fl= ags) igt_require(gem_mmap__has_wc(fd)); switch (scale) { case 0: - size =3D gem_mappable_aperture_size() + 4096; + size =3D gem_mappable_aperture_size(fd) + 4096; break; case 1: size =3D gem_global_aperture_size(fd) + 4096; @@ -257,7 +257,7 @@ static void test_random(int fd) gem_require_mmap_wc(fd); size =3D min(intel_get_total_ram_mb() / 2, - gem_mappable_aperture_size() + 4096); + gem_mappable_aperture_size(fd) + 4096); intel_require_memory(1, size, CHECK_RAM); handle =3D gem_create(fd, size); diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c index dba62c8fa..023db8c56 100644 --- a/tests/i915/gem_shrink.c +++ b/tests/i915/gem_shrink.c @@ -439,7 +439,7 @@ igt_main * we expect the shrinker to start purging objects, * and possibly fail. */ - alloc_size =3D gem_mappable_aperture_size() / 2; + alloc_size =3D gem_mappable_aperture_size(fd) / 2; num_processes =3D 1 + (mem_size / (alloc_size >> 20)); igt_info("Using %d processes and %'lluMiB per process\n", diff --git a/tests/i915/gem_tiled_fence_blits.c b/tests/i915/gem_tiled_fenc= e_blits.c index 0a633d91b..28beea898 100644 --- a/tests/i915/gem_tiled_fence_blits.c +++ b/tests/i915/gem_tiled_fence_blits.c @@ -225,7 +225,7 @@ igt_main gem_require_blitter(fd); gem_require_mappable_ggtt(fd); - count =3D gem_mappable_aperture_size(); /* thrash fences! *= / + count =3D gem_mappable_aperture_size(fd); /* thrash fences!= */ if (count >> 32) count =3D MAX_32b; count =3D 3 + count / (1024 * 1024); diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c index 6d46c320c..6321dd403 100644 --- a/tests/i915/i915_pm_rpm.c +++ b/tests/i915/i915_pm_rpm.c @@ -1419,7 +1419,7 @@ static void gem_evict_pwrite_subtest(void) unsigned int num_trash_bos, n; uint32_t buf; - num_trash_bos =3D gem_mappable_aperture_size() / (1024*1024) + 1; + num_trash_bos =3D gem_mappable_aperture_size(drm_fd) / (1024*1024) = + 1; trash_bos =3D malloc(num_trash_bos * sizeof(*trash_bos)); igt_assert(trash_bos); @@ -1463,7 +1463,7 @@ static bool device_in_pci_d3(void) uint16_t val; int rc; - rc =3D pci_device_cfg_read_u16(intel_get_pci_device(), &val, 0xd4); + rc =3D pci_device_cfg_read_u16(igt_device_get_pci_device(drm_fd), &= val, 0xd4); igt_assert_eq(rc, 0); igt_debug("%s: PCI D3 state=3D%d\n", __func__, val & 0x3); diff --git a/tests/kms_big_fb.c b/tests/kms_big_fb.c index 02e9915ba..8794ace08 100644 --- a/tests/kms_big_fb.c +++ b/tests/kms_big_fb.c @@ -645,7 +645,7 @@ igt_main data.ram_size =3D intel_get_total_ram_mb() << 20; data.aper_size =3D gem_aperture_size(data.drm_fd); - data.mappable_size =3D gem_mappable_aperture_size(); + data.mappable_size =3D gem_mappable_aperture_size(data.drm_= fd); igt_info("RAM: %"PRIu64" MiB, GPU address space: %"PRId64"= MiB, GGTT mappable size: %"PRId64" MiB\n", data.ram_size >> 20, data.aper_size >> 20, diff --git a/tests/kms_flip.c b/tests/kms_flip.c index 51b9ac950..0f0565cf6 100755 --- a/tests/kms_flip.c +++ b/tests/kms_flip.c @@ -1282,7 +1282,7 @@ static void __run_test_on_crtc_set(struct test_output= *o, int *crtc_idxs, /* 256 MB is usually the maximum mappable aperture, * (make it 4x times that to ensure failure) */ if (o->flags & TEST_BO_TOOBIG) { - bo_size =3D 4*gem_mappable_aperture_size(); + bo_size =3D 4*gem_mappable_aperture_size(drm_fd); igt_require(bo_size < gem_global_aperture_size(drm_fd)); } diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c index 143342410..7c43ced85 100644 --- a/tests/prime_mmap.c +++ b/tests/prime_mmap.c @@ -447,8 +447,8 @@ test_aperture_limit(void) char *ptr1, *ptr2; uint32_t handle1, handle2; /* Two buffers the sum of which > mappable aperture */ - uint64_t size1 =3D (gem_mappable_aperture_size() * 7) / 8; - uint64_t size2 =3D (gem_mappable_aperture_size() * 3) / 8; + uint64_t size1 =3D (gem_mappable_aperture_size(fd) * 7) / 8; + uint64_t size2 =3D (gem_mappable_aperture_size(fd) * 3) / 8; handle1 =3D gem_create(fd, size1); fill_bo(handle1, BO_SIZE); -- 2.29.2 --_000_7021dc5149a24438878f6540a0c4aed8intelcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Some minor comments as below.


Reviewed-by: Bruce Chang <yu.bruce.chang@intel.com>

From: Chris Wilson <ch= ris@chris-wilson.co.uk>
Sent: Saturday, December 12, 2020 1:43 AM
To: intel-gfx@lists.freedesktop.org
Cc: igt-dev@lists.freedesktop.org; Chris Wilson; Chang, Yu bruce
Subject: [PATCH i-g-t] lib: Pass device fd to gem_mmappable_aperture= _size()
 
In order to find the co= rrect aperture size for the test, we want to pass
the test's device into the query.

Reported-by: Bruce Chang <yu.bruce.chang@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Bruce Chang <yu.bruce.chang@intel.com>
---
 lib/i915/gem_mman.c        &n= bsp;       | 108 +++++= 3;++++++++++++++= 3;++++++
 lib/i915/gem_mman.h        &n= bsp;       |   6 ++
 lib/ioctl_wrappers.c        &= nbsp;      | 116 -----------------------------
 lib/ioctl_wrappers.h        &= nbsp;      |   5 --
 tests/i915/gem_concurrent_all.c    |  12 +--<= br>  tests/i915/gem_mmap.c        =       |   4 +-
 tests/i915/gem_mmap_gtt.c       &n= bsp;  |  10 +--
 tests/i915/gem_pwrite.c       &nbs= p;    |   6 +-
 tests/i915/gem_shrink.c       &nbs= p;    |   2 +-
 tests/i915/gem_tiled_fence_blits.c |   2 +-
 tests/i915/i915_pm_rpm.c       &nb= sp;   |   4 +-
 tests/kms_big_fb.c        &nb= sp;        |   2 +-
 tests/kms_flip.c         = ;          |   2 = 3;-
 tests/prime_mmap.c        &nb= sp;        |   4 +-
 14 files changed, 138 insertions(+), 145 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 93bef2bfc..703c6a5c1 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -27,7 +27,9 @@
 #include <errno.h>
 
 #include "igt_core.h"
+#include "igt_device.h"
 #include "ioctl_wrappers.h"
+#include "intel_chipset.h"
 
 #include "gem_mman.h"
 
@@ -551,3 +553,109 @@ const struct mmap_offset mmap_offset_types[] =3D = {
         { "uc", I915_MMA= P_OFFSET_UC, I915_GEM_DOMAIN_WC },
         {},
 };
+
+/**
+ * gem_available_aperture_size:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query the kernel for the available gpu apertu= re size
+ * usable in a batchbuffer.
+ *
+ * Returns: The available gtt address space size.
+ */
+uint64_t gem_available_aperture_size(int fd)
+{
+       struct drm_i915_gem_get_aperture = aperture =3D {
+           &nbs= p;   aperture.aper_available_size =3D 256*1024*1024,
+       };
+
+       ioctl(fd, DRM_IOCTL_I915_GEM_GET_= APERTURE, &aperture);
+       errno =3D 0;
+
+       return aperture.aper_available_si= ze;
+}
+
+/**
+ * gem_aperture_size:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query the kernel for the total gpu aperture s= ize.
+ *
+ * Returns: The total gtt address space size.
+ */
+uint64_t gem_aperture_size(int fd)
+{
+       struct drm_i915_gem_context_param= p =3D {
+           &nbs= p;   .param =3D 0x3
+       };

Understand this is the = original code, but it will be more readable to use I915_CONTEXT_= PARAM_GTT_SIZE instead of 3.

+
+       if (__gem_context_get_param(fd, &= amp;p))
+           &nbs= p;   p.value =3D gem_global_aperture_size(fd);
+
+       return p.value;
+}
+
+/**
+ * gem_mappable_aperture_size:
+ *
+ * Feature test macro to query the kernel for the mappable gpu apertur= e size.
+ * This is the area available for GTT memory mappings.
+ *
+ * Returns: The mappable gtt address space size.
+ */
+uint64_t gem_mappable_aperture_size(int fd)
+{
+       struct pci_device *pci_dev =3D ig= t_device_get_pci_device(fd);

Does it m= ake sense to eliminate the function intel_get_pci_device() if not being u= sed anymore? But it can be a separate patch.
<= br> +     =   int bar;
+
+       = if (intel_gen(pci_dev->device_id) < 3)
+      &= nbsp;        bar =3D 0;
+       = else
+      &= nbsp;        bar =3D 2;
+
+       = return pci_dev->regions[bar].size;
+}
+
+/**
+ * gem_global_aperture_size: + * @fd: open i915 drm file descriptor=
+ *
+ * Feature test macro to query the ke= rnel for the global gpu aperture size.
+ * This is the area available for the= kernel to perform address translations.
+ *
+ * Returns: The gtt address space siz= e.
+ */
+uint64_t gem_global_aperture_size(int= fd)
+{
+       = struct drm_i915_gem_get_aperture aperture =3D {
+      &= nbsp;        aperture.aper_size =3D 256*= 1024*1024
+       = };
+
+       = ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+       = errno =3D 0;
+
+       = return aperture.aper_size;
+}
+
+/**
+ * gem_available_fences:
+ * @fd: open i915 drm file descriptor=
+ *
+ * Feature test macro to query the ke= rnel for the number of available fences
+ * usable in a batchbuffer. Only rele= vant for pre-gen4.
+ *
+ * Returns: The number of available f= ences.
+ */
+int gem_available_fences(int fd)
+{
+       = int num_fences =3D 0;
+       = struct drm_i915_getparam gp =3D {
+      &= nbsp;        gp.param =3D I915_PARAM_NUM= _FENCES_AVAIL,
+      &= nbsp;        gp.value =3D &num_fence= s,
+       = };
+
+       = ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
+       = errno =3D 0;
+
+       = return num_fences;
+}
diff --git a/lib/i915/gem_mman.h b/lib/i91= 5/gem_mman.h
index 2c4a7a00b..ec2899ffe 100644 --- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -109,5 +109,11 @@ bool gem_has_mmap= _offset_type(int fd, const struct mmap_offset *t);
       =        (__t)++) \
       =           for_each_if(gem_has_= mmap_offset_type((fd), (__t)))
 
+uint64_t gem_available_aperture_size(= int fd);
+uint64_t gem_aperture_size(int fd);
+uint64_t gem_global_aperture_size(int= fd);
+uint64_t gem_mappable_aperture_size(i= nt fd);
+int gem_available_fences(int fd);
+
 #endif /* GEM_MMAN_H */
 
diff --git a/lib/ioctl_wrappers.c b/lib/io= ctl_wrappers.c
index 06431ce6c..a928f894f 100644 --- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -782,31 +782,6 @@ bool gem_engine_r= eset_enabled(int fd)
       =   return gem_gpu_reset_type(fd) > 1;
 }
 
-/**
- * gem_available_fences:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the number of available fences
- * usable in a batchbuffer. Only relevant= for pre-gen4.
- *
- * Returns: The number of available fence= s.
- */
-int gem_available_fences(int fd) -{
-       int = num_fences;
-       stru= ct drm_i915_getparam gp;
-
-       mems= et(&gp, 0, sizeof(gp));
-       gp.p= aram =3D I915_PARAM_NUM_FENCES_AVAIL;
-       gp.v= alue =3D &num_fences;
-
-       num_= fences =3D 0;
-       ioct= l(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
-       errn= o =3D 0;
-
-       retu= rn num_fences;
-}
-
 bool gem_has_llc(int fd)
 {
       =   int has_llc;
@@ -929,97 +904,6 @@ uint64_t gem_tota= l_stolen_size(int fd)
       =   return aperture.stolen_total_size;
 }
 
-/**
- * gem_available_aperture_size: - * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the available gpu aperture size
- * usable in a batchbuffer.
- *
- * Returns: The available gtt address spa= ce size.
- */
-uint64_t gem_available_aperture_size(int = fd)
-{
-       stru= ct drm_i915_gem_get_aperture aperture;
-
-       mems= et(&aperture, 0, sizeof(aperture));
-       aper= ture.aper_size =3D 256*1024*1024;
-       do_i= octl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
-
-       retu= rn aperture.aper_available_size;
-}
-
-/**
- * gem_aperture_size:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the total gpu aperture size.
- *
- * Returns: The total gtt address space s= ize.
- */
-uint64_t gem_aperture_size(int fd)=
-{
-       uint= 64_t aperture_size =3D 0;
-       stru= ct drm_i915_gem_context_param p;
-
-       mems= et(&p, 0, sizeof(p));
-       p.pa= ram =3D 0x3;
-       if (= __gem_context_get_param(fd, &p) =3D=3D 0) {
-       = ;        aperture_size =3D p.value;
-       } el= se {
-       = ;        struct drm_i915_gem_get_apertur= e aperture;
-
-       = ;        memset(&aperture, 0, sizeof= (aperture));
-       = ;        aperture.aper_size =3D 256*1024= *1024;
-
-       = ;        do_ioctl(fd, DRM_IOCTL_I915_GEM= _GET_APERTURE, &aperture);
-       = ;        aperture_size =3D  apertur= e.aper_size;
-       }
-
-       retu= rn aperture_size;
-}
-
-/**
- * gem_mappable_aperture_size:
- *
- * Feature test macro to query the kernel= for the mappable gpu aperture size.
- * This is the area available for GTT mem= ory mappings.
- *
- * Returns: The mappable gtt address spac= e size.
- */
-uint64_t gem_mappable_aperture_size(void)=
-{
-       stru= ct pci_device *pci_dev =3D intel_get_pci_device();
-       int = bar;
-
-       if (= intel_gen(pci_dev->device_id) < 3)
-       = ;        bar =3D 0;
-       else=
-       = ;        bar =3D 2;
-
-       retu= rn pci_dev->regions[bar].size;
-}
-
-/**
- * gem_global_aperture_size:
- * @fd: open i915 drm file descriptor
- *
- * Feature test macro to query the kernel= for the global gpu aperture size.
- * This is the area available for the ker= nel to perform address translations.
- *
- * Returns: The gtt address space size.
- */
-uint64_t gem_global_aperture_size(int fd)=
-{
-       stru= ct drm_i915_gem_get_aperture aperture;
-
-       mems= et(&aperture, 0, sizeof(aperture));
-       aper= ture.aper_size =3D 256*1024*1024;
-       do_i= octl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
-
-       retu= rn aperture.aper_size;
-}
-
 /**
  * gem_has_softpin:
  * @fd: open i915 drm file descripto= r
diff --git a/lib/ioctl_wrappers.h b/lib/io= ctl_wrappers.h
index b76bea564..07879ae96 100644 --- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -117,12 +117,7 @@ bool gem_uses_ful= l_ppgtt(int fd);
 int gem_gpu_reset_type(int fd);
 bool gem_gpu_reset_enabled(int fd);<= /span>
 bool gem_engine_reset_enabled(int fd= );
-int gem_available_fences(int fd);<= br>  uint64_t gem_total_stolen_size(int f= d);
-uint64_t gem_available_aperture_size(int = fd);
-uint64_t gem_aperture_size(int fd);
-uint64_t gem_global_aperture_size(int fd)= ;
-uint64_t gem_mappable_aperture_size(void)= ;
 bool gem_has_softpin(int fd);=
 bool gem_has_exec_fence(int fd);
 
diff --git a/tests/i915/gem_concurrent_all= .c b/tests/i915/gem_concurrent_all.c
index 9ea94125e..da850a104 100644 --- a/tests/i915/gem_concurrent_all.c
+++ b/tests/i915/gem_concurren= t_all.c
@@ -1828,7 +1828,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "small");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size()/4,
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd)/4,
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
@@ -1839,7 +1839,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "thrash");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
@@ -1871,7 +1871,7 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "shrink");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM);
 
       =             &nb= sp;            =          igt_fork_shrink_helper(fd)= ;
@@ -1887,8 +1887,8 @@ igt_main<= br>        =             &nb= sp;            =   c->name, s->name, "swap");
       =             &nb= sp;     igt_subtest_group {
       =             &nb= sp;            = igt_fixture {
-       = ;            &n= bsp;            = ;       if (intel_get_avail_ram_mb() > gem= _mappable_aperture_size()/(1024*1024)) {
-       = ;            &n= bsp;            = ;            &n= bsp;  pin_sz =3D intel_get_avail_ram_mb() - gem_mappable_aperture_size= ()/(1024*1024);
+      &= nbsp;           &nbs= p;            &= nbsp;       if (intel_get_avail_ram_mb() >= gem_mappable_aperture_size(fd)/(1024*1024)) {
+      &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;   pin_sz =3D intel_get_avail_ram_mb() - gem_mappable_aperture_= size(fd)/(1024*1024);
 
       =             &nb= sp;            =             &nb= sp;    igt_debug("Pinning %lld MiB\n", (long long)= pin_sz);
       =             &nb= sp;            =             &nb= sp;    pin_sz *=3D 1024 * 1024;
@@ -1902,7 +1902,7 @@ igt_main<= br>        =             &nb= sp;            =             &nb= sp;    igt_require(pinned);
       =             &nb= sp;            =          }
 
-       = ;            &n= bsp;            = ;       count =3D num_buffers(gem_mappable_ap= erture_size(),
+      &= nbsp;           &nbs= p;            &= nbsp;       count =3D num_buffers(gem_mappabl= e_aperture_size(fd),
       =             &nb= sp;            =             &nb= sp;            =     s, c, CHECK_RAM | CHECK_SWAP);
       =             &nb= sp;            = }
       =             &nb= sp;            = run_modes(name, c, modes, s, count);
diff --git a/tests/i915/gem_mmap.c b/tests= /i915/gem_mmap.c
index 8bad9b14e..60a64c134 100644 --- a/tests/i915/gem_mmap.c
+++ b/tests/i915/gem_mmap.c
@@ -53,10 +53,10 @@ test_huge_bo(int h= uge)
 
       =   switch (huge) {
       =   case -1:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 2;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 2;
       =           break;
       =   case 0:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() + PAGE_SIZE;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) + PAGE_SIZE;
       =           break;
       =   case 1:
       =           huge_object_size =3D= gem_aperture_size(fd) + PAGE_SIZE;
diff --git a/tests/i915/gem_mmap_gtt.c b/t= ests/i915/gem_mmap_gtt.c
index 61fbc5bc7..528a7c726 100644 --- a/tests/i915/gem_mmap_gtt.c
+++ b/tests/i915/gem_mmap_gtt.= c
@@ -905,7 +905,7 @@ test_huge_bo(int f= d, int huge, int tiling)
 
       =   switch (huge) {
       =   case -1:
-       = ;        size =3D gem_mappable_aperture_= size() / 2;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) / 2;
 
       =           /* Power of two fenc= e size, natural fence
       =            * alignment, a= nd the guard page at the end
@@ -920,7 +920,7 @@ test_huge_bo(int f= d, int huge, int tiling)
       =             &nb= sp;     size /=3D 2;
       =           break;
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + PAGE_SIZE;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + PAGE_SIZE;
       =           break;
       =   default:
       =           size =3D gem_global_= aperture_size(fd) + PAGE_SIZE;
@@ -1001,13 +1001,13 @@ test_huge_copy= (int fd, int huge, int tiling_a, int tiling_b, int ncpus)
 
       =   switch (huge) {
       =   case -2:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 4;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 4;
       =           break;
       =   case -1:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() / 2;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) / 2;
       =           break;
       =   case 0:
-       = ;        huge_object_size =3D gem_mappab= le_aperture_size() + PAGE_SIZE;
+      &= nbsp;        huge_object_size =3D gem_ma= ppable_aperture_size(fd) + PAGE_SIZE;
       =           break;
       =   case 1:
       =           huge_object_size =3D= gem_global_aperture_size(fd) + PAGE_SIZE;
diff --git a/tests/i915/gem_pwrite.c b/tes= ts/i915/gem_pwrite.c
index d2dcc95e8..f76d2bc70 100644 --- a/tests/i915/gem_pwrite.c
+++ b/tests/i915/gem_pwrite.c<= /span>
@@ -130,7 +130,7 @@ static void test_b= ig_cpu(int fd, int scale, unsigned flags)
 
       =   switch (scale) {
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + 4096;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + 4096;
       =           break;
       =   case 1:
       =           size =3D gem_global_= aperture_size(fd) + 4096;
@@ -192,7 +192,7 @@ static void test_b= ig_gtt(int fd, int scale, unsigned flags)
       =   igt_require(gem_mmap__has_wc(fd));
       =   switch (scale) {
       =   case 0:
-       = ;        size =3D gem_mappable_aperture_= size() + 4096;
+      &= nbsp;        size =3D gem_mappable_apert= ure_size(fd) + 4096;
       =           break;
       =   case 1:
       =           size =3D gem_global_= aperture_size(fd) + 4096;
@@ -257,7 +257,7 @@ static void test_r= andom(int fd)
       =   gem_require_mmap_wc(fd);
 
       =   size =3D min(intel_get_total_ram_mb() / 2,
-       = ;            gem_map= pable_aperture_size() + 4096);
+      &= nbsp;            gem= _mappable_aperture_size(fd) + 4096);
       =   intel_require_memory(1, size, CHECK_RAM);
 
       =   handle =3D gem_create(fd, size);
diff --git a/tests/i915/gem_shrink.c b/tes= ts/i915/gem_shrink.c
index dba62c8fa..023db8c56 100644 --- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c<= /span>
@@ -439,7 +439,7 @@ igt_main        =            * we expect th= e shrinker to start purging objects,
       =            * and possibly= fail.
       =            */
-       = ;        alloc_size =3D gem_mappable_ape= rture_size() / 2;
+      &= nbsp;        alloc_size =3D gem_mappable= _aperture_size(fd) / 2;
       =           num_processes =3D 1 = + (mem_size / (alloc_size >> 20));
 
       =           igt_info("Using= %d processes and %'lluMiB per process\n",
diff --git a/tests/i915/gem_tiled_fence_bl= its.c b/tests/i915/gem_tiled_fence_blits.c
index 0a633d91b..28beea898 100644 --- a/tests/i915/gem_tiled_fence_blits.c
+++ b/tests/i915/gem_tiled_fen= ce_blits.c
@@ -225,7 +225,7 @@ igt_main        =           gem_require_blitter(= fd);
       =           gem_require_mappable= _ggtt(fd);
 
-       = ;        count =3D gem_mappable_aperture= _size(); /* thrash fences! */
+      &= nbsp;        count =3D gem_mappable_aper= ture_size(fd); /* thrash fences! */
       =           if (count >> 3= 2)
       =             &nb= sp;     count =3D MAX_32b;
       =           count =3D 3 + co= unt / (1024 * 1024);
diff --git a/tests/i915/i915_pm_rpm.c b/te= sts/i915/i915_pm_rpm.c
index 6d46c320c..6321dd403 100644 --- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c=
@@ -1419,7 +1419,7 @@ static void gem_= evict_pwrite_subtest(void)
       =   unsigned int num_trash_bos, n;
       =   uint32_t buf;
 
-       num_= trash_bos =3D gem_mappable_aperture_size() / (1024*1024) + 1; +       = num_trash_bos =3D gem_mappable_aperture_size(drm_fd) / (1024*1024) + 1;=
       =   trash_bos =3D malloc(num_trash_bos * sizeof(*trash_bos));
       =   igt_assert(trash_bos);
 
@@ -1463,7 +1463,7 @@ static bool devi= ce_in_pci_d3(void)
       =   uint16_t val;
       =   int rc;
 
-       rc = =3D pci_device_cfg_read_u16(intel_get_pci_device(), &val, 0xd4);=
+       = rc =3D pci_device_cfg_read_u16(igt_device_get_pci_device(drm_fd), &val,= 0xd4);
       =   igt_assert_eq(rc, 0);
 
       =   igt_debug("%s: PCI D3 state=3D%d\n", __func__, val & 0= x3);
diff --git a/tests/kms_big_fb.c b/tests/km= s_big_fb.c
index 02e9915ba..8794ace08 100644 --- a/tests/kms_big_fb.c
+++ b/tests/kms_big_fb.c
@@ -645,7 +645,7 @@ igt_main  
       =           data.ram_size =3D in= tel_get_total_ram_mb() << 20;
       =           data.aper_size =3D g= em_aperture_size(data.drm_fd);
-       = ;        data.mappable_size =3D gem_mapp= able_aperture_size();
+      &= nbsp;        data.mappable_size =3D gem_= mappable_aperture_size(data.drm_fd);
 
       =           igt_info("RAM: = %"PRIu64" MiB, GPU address space: %"PRId64" MiB, GGTT m= appable size: %"PRId64" MiB\n",
       =             &nb= sp;      data.ram_size >> 20, data.aper_size= >> 20,
diff --git a/tests/kms_flip.c b/tests/kms_= flip.c
index 51b9ac950..0f0565cf6 100755 --- a/tests/kms_flip.c
+++ b/tests/kms_flip.c<= br> @@ -1282,7 +1282,7 @@ static void __ru= n_test_on_crtc_set(struct test_output *o, int *crtc_idxs,
       =   /* 256 MB is usually the maximum mappable aperture,
       =    * (make it 4x times that to ensure failure) */
       =   if (o->flags & TEST_BO_TOOBIG) {
-       = ;        bo_size =3D 4*gem_mappable_aper= ture_size();
+      &= nbsp;        bo_size =3D 4*gem_mappable_= aperture_size(drm_fd);
       =           igt_require(bo_size = < gem_global_aperture_size(drm_fd));
       =   }
 
diff --git a/tests/prime_mmap.c b/tests/pr= ime_mmap.c
index 143342410..7c43ced85 100644 --- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -447,8 +447,8 @@ test_aperture_limi= t(void)
       =   char *ptr1, *ptr2;
       =   uint32_t handle1, handle2;
       =   /* Two buffers the sum of which > mappable aperture */
-       uint= 64_t size1 =3D (gem_mappable_aperture_size() * 7) / 8;
-       uint= 64_t size2 =3D (gem_mappable_aperture_size() * 3) / 8;
+       = uint64_t size1 =3D (gem_mappable_aperture_size(fd) * 7) / 8;
+       = uint64_t size2 =3D (gem_mappable_aperture_size(fd) * 3) / 8;
 
       =   handle1 =3D gem_create(fd, size1);
       =   fill_bo(handle1, BO_SIZE);
--
2.29.2

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