From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93B25C47249 for ; Thu, 3 Jun 2021 07:44:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 770D7613D6 for ; Thu, 3 Jun 2021 07:44:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbhFCHqT (ORCPT ); Thu, 3 Jun 2021 03:46:19 -0400 Received: from mga07.intel.com ([134.134.136.100]:33539 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbhFCHqI (ORCPT ); Thu, 3 Jun 2021 03:46:08 -0400 IronPort-SDR: Z1+FTwZr2RC918Mq/nfBfPN3+VGBGdvhX0kQTMjcXa1vKkH6X6sHSjvQ29Kc42D9VHYjShofAw Sp+Ja65Bl8mw== X-IronPort-AV: E=McAfee;i="6200,9189,10003"; a="267854783" X-IronPort-AV: E=Sophos;i="5.83,244,1616482800"; d="scan'208";a="267854783" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 00:44:18 -0700 IronPort-SDR: Fa9tuxN+YCQm1gSvXYwJ75hkfxMjcqJgNzlZfgMsyUZnZztwYUYS14R6jb/vsEHWHWrZeP9IdX CunYAri108kQ== X-IronPort-AV: E=Sophos;i="5.83,244,1616482800"; d="scan'208";a="480082123" Received: from shao2-debian.sh.intel.com (HELO [10.239.13.11]) ([10.239.13.11]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2021 00:44:14 -0700 Subject: Re: [tip:x86/cpu 4/4] Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111< /* free ( 3*32+29) */ To: Arnaldo Carvalho de Melo , Borislav Petkov Cc: Andrew Cooper , kbuild-all@lists.01.org, linux-kernel@vger.kernel.org, x86@kernel.org, Peter Zijlstra References: <20210602094153.GH1271937@shao2-debian> From: Rong Chen Message-ID: <70606ff4-cdba-1c44-68c0-69e61c1bf65a@intel.com> Date: Thu, 3 Jun 2021 15:43:59 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/2/21 11:35 PM, Arnaldo Carvalho de Melo wrote: > Em Wed, Jun 02, 2021 at 11:45:42AM +0200, Borislav Petkov escreveu: >> + acme. >> >> On Wed, Jun 02, 2021 at 05:41:53PM +0800, kernel test robot wrote: >>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/cpu >>> head: cbcddaa33d7e11a053cb80a4a635c023b4f8b906 >>> commit: cbcddaa33d7e11a053cb80a4a635c023b4f8b906 [4/4] perf/x86/rapl: Use CPUID bit on AMD and Hygon parts >>> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 >>> reproduce: >>> cd tools/perf && ./check-headers.sh >>> >>> If you fix the issue, kindly add following tag as appropriate >>> Reported-by: kernel test robot >>> >>> >>> perfheadercheck warnings: (new ones prefixed by >>) >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 87< #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 87> /* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ >>>>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111< /* free ( 3*32+29) */ >>>>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111> #define X86_FEATURE_RAPL ( 3*32+29) /* AMD/Hygon RAPL interface */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 239> #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 240> #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempted function */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 295> #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 296> #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 343> #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 362> #define X86_FEATURE_BUS_LOCK_DETECT (16*32+24) /* Bus Lock detect */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 383> #define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs of more than one type */ >>> >>> --- >>> 0-DAY CI Kernel Test Service, Intel Corporation >>> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org >> 0day folks, please make a note if you can, to send such cpufeatures.h >> header sync warnings to acme as he's verifying the feature bits modified >> before synching. >> >> Better yet, you can even ignore those altogether but I'm sure acme has a >> preference here. > Borislav, > > This is an attempt, suggested by PeterZ for us to try to > automate those updates, so what I was expecting wasn't a report that > something changed, as I notice it myself, but an attempt at checking if > the changes in these updates would entail changes in the tools build. > > Say, is there a script in tools/perf/trace/beauty/ that ends up > producing a different .c that then gets compiled/linked with tooling? Or > this is just a trivial change like happens from time to time, a typo > fix, some comments added, etc. > > Some examples of what those scripts do: > > ⬢[acme@toolbox perf]$ tools/perf/trace/beauty/fadvise.sh > static const char *fadvise_advices[] = { > [0] = "NORMAL", > [1] = "RANDOM", > [2] = "SEQUENTIAL", > [3] = "WILLNEED", > [4] = "DONTNEED", > [5] = "NOREUSE", > }; > ⬢[acme@toolbox perf]$ tools/perf/trace/beauty/socket.sh > static const char *socket_families[] = { > [0] = "UNSPEC", > [1] = "LOCAL", > [2] = "INET", > [3] = "AX25", > [4] = "IPX", > [5] = "APPLETALK", > [6] = "NETROM", > [7] = "BRIDGE", > [8] = "ATMPVC", > [9] = "X25", > [10] = "INET6", > [11] = "ROSE", > [12] = "DECnet", > [13] = "NETBEUI", > [14] = "SECURITY", > [15] = "KEY", > [16] = "NETLINK", > [17] = "PACKET", > [18] = "ASH", > [19] = "ECONET", > [20] = "ATMSVC", > [21] = "RDS", > [22] = "SNA", > [23] = "IRDA", > [24] = "PPPOX", > [25] = "WANPIPE", > [26] = "LLC", > [27] = "IB", > [28] = "MPLS", > [29] = "CAN", > [30] = "TIPC", > [31] = "BLUETOOTH", > [32] = "IUCV", > [33] = "RXRPC", > [34] = "ISDN", > [35] = "PHONET", > [36] = "IEEE802154", > [37] = "CAIF", > [38] = "ALG", > [39] = "NFC", > [40] = "VSOCK", > [41] = "KCM", > [42] = "QIPCRTR", > [43] = "SMC", > [44] = "XDP", > }; > ⬢[acme@toolbox perf]$ > > Some of those files are used for building the tools, so that a > tarball generated from: > > ⬢[acme@toolbox perf]$ make help | grep perf > perf-tar-src-pkg - Build perf-5.13.0-rc4.tar source tarball > perf-targz-src-pkg - Build perf-5.13.0-rc4.tar.gz source tarball > perf-tarbz2-src-pkg - Build perf-5.13.0-rc4.tar.bz2 source tarball > perf-tarxz-src-pkg - Build perf-5.13.0-rc4.tar.xz source tarball > ⬢[acme@toolbox perf]$ > > will build in older systems where things added to the updated copy of > the kernel headers isn't present, so trying to update the file and then > rebuild perf, only warning me if it doesn't build would give me an early > warning about things that are breaking and that I should look sooner > rather than later. Hi Arnaldo, Thanks for the detailed explanation, I'm a little confused, do you mean we should both rebuild perf with the updated kernel headers and check the difference between headers by the scripts in tools/perf/trace/beauty? Best Regards, Rong Chen > > Doing just the diff is not that useful :-) > > - Arnaldo > > One more output that is x86 specific and allows this to work: > > # perf trace -e msr:* --filter="msr!=FS_BASE && msr != IA32_TSC_DEADLINE && msr != 0x830 && msr != 0x83f && msr !=IA32_SPEC_CTRL" --filter-pids 3750 > 0.000 Timer/5033 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 0.009 Timer/5033 msr:write_msr(msr: LSTAR, val: -1398800368) > 0.010 Timer/5033 msr:write_msr(msr: TSC_AUX, val: 4) > 0.050 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 45.661 gnome-terminal/12595 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 45.672 gnome-terminal/12595 msr:write_msr(msr: LSTAR, val: -1398800368) > 45.675 gnome-terminal/12595 msr:write_msr(msr: TSC_AUX, val: 3) > 54.852 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 130.508 Timer/4050 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 130.527 Timer/4050 msr:write_msr(msr: LSTAR, val: -1398800368) > 130.531 Timer/4050 msr:write_msr(msr: TSC_AUX, val: 3) > 140.924 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 164.738 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 603.578 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 620.809 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 690.115 JS Watchdog/4259 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 690.136 JS Watchdog/4259 msr:write_msr(msr: LSTAR, val: -1398800368) > 690.141 JS Watchdog/4259 msr:write_msr(msr: TSC_AUX, val: 3) > 690.186 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 759.016 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > ^C[root@quaco ~]# > > Or look at the first 3 write_msr events for that IA32_TSC_DEADLINE to learn why > it happens so often: > > # perf trace --max-events=3 --max-stack=8 -e msr:* --filter="msr==IA32_TSC_DEADLINE" --filter-pids 3750 > 0.000 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 19296732550862) > do_trace_write_msr ([kernel.kallsyms]) > do_trace_write_msr ([kernel.kallsyms]) > lapic_next_deadline ([kernel.kallsyms]) > clockevents_program_event ([kernel.kallsyms]) > hrtimer_interrupt ([kernel.kallsyms]) > smp_apic_timer_interrupt ([kernel.kallsyms]) > apic_timer_interrupt ([kernel.kallsyms]) > cpuidle_enter_state ([kernel.kallsyms]) > 32.646 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 19296800134158) > do_trace_write_msr ([kernel.kallsyms]) > do_trace_write_msr ([kernel.kallsyms]) > lapic_next_deadline ([kernel.kallsyms]) > clockevents_program_event ([kernel.kallsyms]) > hrtimer_start_range_ns ([kernel.kallsyms]) > tick_nohz_restart_sched_tick ([kernel.kallsyms]) > tick_nohz_idle_exit ([kernel.kallsyms]) > do_idle ([kernel.kallsyms]) > 32.802 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 19297507436922) > do_trace_write_msr ([kernel.kallsyms]) > do_trace_write_msr ([kernel.kallsyms]) > lapic_next_deadline ([kernel.kallsyms]) > clockevents_program_event ([kernel.kallsyms]) > hrtimer_try_to_cancel ([kernel.kallsyms]) > hrtimer_cancel ([kernel.kallsyms]) > tick_nohz_restart_sched_tick ([kernel.kallsyms]) > tick_nohz_idle_exit ([kernel.kallsyms]) > # > > > > ⬢[acme@toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_msr.sh > static const char *x86_MSRs[] = { > [0x00000000] = "IA32_P5_MC_ADDR", > [0x00000001] = "IA32_P5_MC_TYPE", > [0x00000010] = "IA32_TSC", > [0x00000017] = "IA32_PLATFORM_ID", > [0x0000001b] = "IA32_APICBASE", > [0x00000020] = "KNC_PERFCTR0", > [0x00000021] = "KNC_PERFCTR1", > [0x00000028] = "KNC_EVNTSEL0", > [0x00000029] = "KNC_EVNTSEL1", > [0x0000002a] = "IA32_EBL_CR_POWERON", > [0x0000002c] = "EBC_FREQUENCY_ID", > [0x00000033] = "TEST_CTRL", > [0x00000034] = "SMI_COUNT", > [0x0000003a] = "IA32_FEAT_CTL", > [0x0000003b] = "IA32_TSC_ADJUST", > [0x00000040] = "LBR_CORE_FROM", > [0x00000048] = "IA32_SPEC_CTRL", > [0x00000049] = "IA32_PRED_CMD", > [0x0000004e] = "PPIN_CTL", > [0x0000004f] = "PPIN", > [0x00000060] = "LBR_CORE_TO", > [0x00000079] = "IA32_UCODE_WRITE", > [0x0000008b] = "AMD64_PATCH_LEVEL", > [0x0000008C] = "IA32_SGXLEPUBKEYHASH0", > [0x0000008D] = "IA32_SGXLEPUBKEYHASH1", > [0x0000008E] = "IA32_SGXLEPUBKEYHASH2", > [0x0000008F] = "IA32_SGXLEPUBKEYHASH3", > [0x0000009b] = "IA32_SMM_MONITOR_CTL", > [0x0000009e] = "IA32_SMBASE", > [0x000000c1] = "IA32_PERFCTR0", > [0x000000c2] = "IA32_PERFCTR1", > [0x000000cd] = "FSB_FREQ", > [0x000000ce] = "PLATFORM_INFO", > [0x000000cf] = "IA32_CORE_CAPS", > [0x000000e2] = "PKG_CST_CONFIG_CONTROL", > [0x000000e7] = "IA32_MPERF", > [0x000000e8] = "IA32_APERF", > [0x000000fe] = "MTRRcap", > [0x00000107] = "IDT_FCR1", > [0x00000108] = "IDT_FCR2", > [0x00000109] = "IDT_FCR3", > [0x0000010a] = "IA32_ARCH_CAPABILITIES", > [0x0000010b] = "IA32_FLUSH_CMD", > [0x0000010F] = "TSX_FORCE_ABORT", > [0x00000110] = "IDT_MCR0", > [0x00000111] = "IDT_MCR1", > [0x00000112] = "IDT_MCR2", > [0x00000113] = "IDT_MCR3", > [0x00000114] = "IDT_MCR4", > [0x00000115] = "IDT_MCR5", > [0x00000116] = "IDT_MCR6", > [0x00000117] = "IDT_MCR7", > [0x00000119] = "IA32_BBL_CR_CTL", > [0x0000011e] = "IA32_BBL_CR_CTL3", > [0x00000120] = "IDT_MCR_CTRL", > [0x00000122] = "IA32_TSX_CTRL", > [0x00000123] = "IA32_MCU_OPT_CTRL", > [0x00000140] = "MISC_FEATURES_ENABLES", > [0x00000174] = "IA32_SYSENTER_CS", > [0x00000175] = "IA32_SYSENTER_ESP", > [0x00000176] = "IA32_SYSENTER_EIP", > [0x00000179] = "IA32_MCG_CAP", > [0x0000017a] = "IA32_MCG_STATUS", > [0x0000017b] = "IA32_MCG_CTL", > [0x0000017f] = "ERROR_CONTROL", > [0x00000180] = "IA32_MCG_EAX", > [0x00000181] = "IA32_MCG_EBX", > [0x00000182] = "IA32_MCG_ECX", > [0x00000183] = "IA32_MCG_EDX", > [0x00000184] = "IA32_MCG_ESI", > [0x00000185] = "IA32_MCG_EDI", > [0x00000186] = "IA32_MCG_EBP", > [0x00000187] = "IA32_MCG_ESP", > [0x00000188] = "IA32_MCG_EFLAGS", > [0x00000189] = "IA32_MCG_EIP", > [0x0000018a] = "IA32_MCG_RESERVED", > [0x00000198] = "IA32_PERF_STATUS", > [0x00000199] = "IA32_PERF_CTL", > [0x0000019a] = "IA32_THERM_CONTROL", > [0x0000019b] = "IA32_THERM_INTERRUPT", > [0x0000019c] = "IA32_THERM_STATUS", > [0x0000019d] = "THERM2_CTL", > [0x000001a0] = "IA32_MISC_ENABLE", > [0x000001a2] = "IA32_TEMPERATURE_TARGET", > [0x000001a4] = "MISC_FEATURE_CONTROL", > [0x000001a6] = "OFFCORE_RSP_0", > [0x000001a7] = "OFFCORE_RSP_1", > [0x000001aa] = "MISC_PWR_MGMT", > [0x000001ad] = "TURBO_RATIO_LIMIT", > [0x000001ae] = "TURBO_RATIO_LIMIT1", > [0x000001af] = "TURBO_RATIO_LIMIT2", > [0x000001b0] = "IA32_ENERGY_PERF_BIAS", > [0x000001b1] = "IA32_PACKAGE_THERM_STATUS", > [0x000001b2] = "IA32_PACKAGE_THERM_INTERRUPT", > [0x000001c8] = "LBR_SELECT", > [0x000001c9] = "LBR_TOS", > [0x000001d9] = "IA32_DEBUGCTLMSR", > [0x000001db] = "IA32_LASTBRANCHFROMIP", > [0x000001dc] = "IA32_LASTBRANCHTOIP", > [0x000001dd] = "IA32_LASTINTFROMIP", > [0x000001de] = "IA32_LASTINTTOIP", > [0x000001fc] = "IA32_POWER_CTL", > [0x00000250] = "MTRRfix64K_00000", > [0x00000258] = "MTRRfix16K_80000", > [0x00000259] = "MTRRfix16K_A0000", > [0x00000268] = "MTRRfix4K_C0000", > [0x00000269] = "MTRRfix4K_C8000", > [0x0000026a] = "MTRRfix4K_D0000", > [0x0000026b] = "MTRRfix4K_D8000", > [0x0000026c] = "MTRRfix4K_E0000", > [0x0000026d] = "MTRRfix4K_E8000", > [0x0000026e] = "MTRRfix4K_F0000", > [0x0000026f] = "MTRRfix4K_F8000", > [0x00000277] = "IA32_CR_PAT", > [0x00000280] = "IA32_MC0_CTL2", > [0x000002ff] = "MTRRdefType", > [0x00000309] = "CORE_PERF_FIXED_CTR0", > [0x0000030a] = "CORE_PERF_FIXED_CTR1", > [0x0000030b] = "CORE_PERF_FIXED_CTR2", > [0x0000030c] = "CORE_PERF_FIXED_CTR3", > [0x00000329] = "PERF_METRICS", > [0x00000345] = "IA32_PERF_CAPABILITIES", > [0x0000038d] = "CORE_PERF_FIXED_CTR_CTRL", > [0x0000038e] = "CORE_PERF_GLOBAL_STATUS", > [0x0000038f] = "CORE_PERF_GLOBAL_CTRL", > [0x00000390] = "CORE_PERF_GLOBAL_OVF_CTRL", > [0x000003f1] = "IA32_PEBS_ENABLE", > [0x000003f2] = "PEBS_DATA_CFG", > [0x000003f6] = "PEBS_LD_LAT_THRESHOLD", > [0x000003f7] = "PEBS_FRONTEND", > [0x000003f8] = "PKG_C3_RESIDENCY", > [0x000003f9] = "PKG_C6_RESIDENCY", > [0x000003fa] = "PKG_C7_RESIDENCY", > [0x000003fc] = "CORE_C3_RESIDENCY", > [0x000003fd] = "CORE_C6_RESIDENCY", > [0x000003fe] = "CORE_C7_RESIDENCY", > [0x000003ff] = "KNL_CORE_C6_RESIDENCY", > [0x00000400] = "IA32_MC0_CTL", > [0x00000401] = "IA32_MC0_STATUS", > [0x00000402] = "IA32_MC0_ADDR", > [0x00000403] = "IA32_MC0_MISC", > [0x00000480] = "IA32_VMX_BASIC", > [0x00000481] = "IA32_VMX_PINBASED_CTLS", > [0x00000482] = "IA32_VMX_PROCBASED_CTLS", > [0x00000483] = "IA32_VMX_EXIT_CTLS", > [0x00000484] = "IA32_VMX_ENTRY_CTLS", > [0x00000485] = "IA32_VMX_MISC", > [0x00000486] = "IA32_VMX_CR0_FIXED0", > [0x00000487] = "IA32_VMX_CR0_FIXED1", > [0x00000488] = "IA32_VMX_CR4_FIXED0", > [0x00000489] = "IA32_VMX_CR4_FIXED1", > [0x0000048a] = "IA32_VMX_VMCS_ENUM", > [0x0000048b] = "IA32_VMX_PROCBASED_CTLS2", > [0x0000048c] = "IA32_VMX_EPT_VPID_CAP", > [0x0000048d] = "IA32_VMX_TRUE_PINBASED_CTLS", > [0x0000048e] = "IA32_VMX_TRUE_PROCBASED_CTLS", > [0x0000048f] = "IA32_VMX_TRUE_EXIT_CTLS", > [0x00000490] = "IA32_VMX_TRUE_ENTRY_CTLS", > [0x00000491] = "IA32_VMX_VMFUNC", > [0x000004c1] = "IA32_PMC0", > [0x000004d0] = "IA32_MCG_EXT_CTL", > [0x00000560] = "IA32_RTIT_OUTPUT_BASE", > [0x00000561] = "IA32_RTIT_OUTPUT_MASK", > [0x00000570] = "IA32_RTIT_CTL", > [0x00000571] = "IA32_RTIT_STATUS", > [0x00000572] = "IA32_RTIT_CR3_MATCH", > [0x00000580] = "IA32_RTIT_ADDR0_A", > [0x00000581] = "IA32_RTIT_ADDR0_B", > [0x00000582] = "IA32_RTIT_ADDR1_A", > [0x00000583] = "IA32_RTIT_ADDR1_B", > [0x00000584] = "IA32_RTIT_ADDR2_A", > [0x00000585] = "IA32_RTIT_ADDR2_B", > [0x00000586] = "IA32_RTIT_ADDR3_A", > [0x00000587] = "IA32_RTIT_ADDR3_B", > [0x00000600] = "IA32_DS_AREA", > [0x00000606] = "RAPL_POWER_UNIT", > [0x0000060a] = "PKGC3_IRTL", > [0x0000060b] = "PKGC6_IRTL", > [0x0000060c] = "PKGC7_IRTL", > [0x0000060d] = "PKG_C2_RESIDENCY", > [0x00000610] = "PKG_POWER_LIMIT", > [0x00000611] = "PKG_ENERGY_STATUS", > [0x00000613] = "PKG_PERF_STATUS", > [0x00000614] = "PKG_POWER_INFO", > [0x00000618] = "DRAM_POWER_LIMIT", > [0x00000619] = "DRAM_ENERGY_STATUS", > [0x0000061b] = "DRAM_PERF_STATUS", > [0x0000061c] = "DRAM_POWER_INFO", > [0x00000630] = "PKG_C8_RESIDENCY", > [0x00000631] = "PKG_C9_RESIDENCY", > [0x00000632] = "PKG_C10_RESIDENCY", > [0x00000633] = "PKGC8_IRTL", > [0x00000634] = "PKGC9_IRTL", > [0x00000635] = "PKGC10_IRTL", > [0x00000638] = "PP0_POWER_LIMIT", > [0x00000639] = "PP0_ENERGY_STATUS", > [0x0000063a] = "PP0_POLICY", > [0x0000063b] = "PP0_PERF_STATUS", > [0x00000640] = "PP1_POWER_LIMIT", > [0x00000641] = "PP1_ENERGY_STATUS", > [0x00000642] = "PP1_POLICY", > [0x00000648] = "CONFIG_TDP_NOMINAL", > [0x00000649] = "CONFIG_TDP_LEVEL_1", > [0x0000064A] = "CONFIG_TDP_LEVEL_2", > [0x0000064B] = "CONFIG_TDP_CONTROL", > [0x0000064C] = "TURBO_ACTIVATION_RATIO", > [0x0000064D] = "PLATFORM_ENERGY_STATUS", > [0x0000064e] = "PPERF", > [0x0000064f] = "PERF_LIMIT_REASONS", > [0x00000658] = "PKG_WEIGHTED_CORE_C0_RES", > [0x00000659] = "PKG_ANY_CORE_C0_RES", > [0x0000065A] = "PKG_ANY_GFXE_C0_RES", > [0x0000065B] = "PKG_BOTH_CORE_GFXE_C0_RES", > [0x00000660] = "CORE_C1_RES", > [0x00000664] = "MODULE_C6_RES_MS", > [0x00000668] = "CC6_DEMOTION_POLICY_CONFIG", > [0x00000669] = "MC6_DEMOTION_POLICY_CONFIG", > [0x00000680] = "LBR_NHM_FROM", > [0x00000690] = "CORE_PERF_LIMIT_REASONS", > [0x000006B0] = "GFX_PERF_LIMIT_REASONS", > [0x000006B1] = "RING_PERF_LIMIT_REASONS", > [0x000006c0] = "LBR_NHM_TO", > [0x00000770] = "PM_ENABLE", > [0x00000771] = "HWP_CAPABILITIES", > [0x00000772] = "HWP_REQUEST_PKG", > [0x00000773] = "HWP_INTERRUPT", > [0x00000774] = "HWP_REQUEST", > [0x00000777] = "HWP_STATUS", > [0x00000d90] = "IA32_BNDCFGS", > [0x00000d93] = "IA32_PASID", > [0x00000da0] = "IA32_XSS", > [0x00000dc0] = "LBR_INFO_0", > [0x00000ffc] = "IA32_BNDCFGS_RSVD", > }; > > #define x86_64_specific_MSRs_offset 0xc0000080 > static const char *x86_64_specific_MSRs[] = { > [0xc0000080 - x86_64_specific_MSRs_offset] = "EFER", > [0xc0000081 - x86_64_specific_MSRs_offset] = "STAR", > [0xc0000082 - x86_64_specific_MSRs_offset] = "LSTAR", > [0xc0000083 - x86_64_specific_MSRs_offset] = "CSTAR", > [0xc0000084 - x86_64_specific_MSRs_offset] = "SYSCALL_MASK", > [0xc0000085 - x86_64_specific_MSRs_offset] = "K6_UWCCR", > [0xc0000086 - x86_64_specific_MSRs_offset] = "K6_EPMR", > [0xc0000087 - x86_64_specific_MSRs_offset] = "K6_PSOR", > [0xc0000088 - x86_64_specific_MSRs_offset] = "K6_PFIR", > [0xc00000e9 - x86_64_specific_MSRs_offset] = "F17H_IRPERF", > [0xc0000100 - x86_64_specific_MSRs_offset] = "FS_BASE", > [0xc0000101 - x86_64_specific_MSRs_offset] = "GS_BASE", > [0xc0000102 - x86_64_specific_MSRs_offset] = "KERNEL_GS_BASE", > [0xc0000103 - x86_64_specific_MSRs_offset] = "TSC_AUX", > [0xc0000104 - x86_64_specific_MSRs_offset] = "AMD64_TSC_RATIO", > }; > > #define x86_AMD_V_KVM_MSRs_offset 0xc0010000 > static const char *x86_AMD_V_KVM_MSRs[] = { > [0xc0010000 - x86_AMD_V_KVM_MSRs_offset] = "K7_EVNTSEL0", > [0xc0010001 - x86_AMD_V_KVM_MSRs_offset] = "K7_EVNTSEL1", > [0xc0010002 - x86_AMD_V_KVM_MSRs_offset] = "K7_EVNTSEL2", > [0xc0010003 - x86_AMD_V_KVM_MSRs_offset] = "K7_EVNTSEL3", > [0xc0010004 - x86_AMD_V_KVM_MSRs_offset] = "K7_PERFCTR0", > [0xc0010005 - x86_AMD_V_KVM_MSRs_offset] = "K7_PERFCTR1", > [0xc0010006 - x86_AMD_V_KVM_MSRs_offset] = "K7_PERFCTR2", > [0xc0010007 - x86_AMD_V_KVM_MSRs_offset] = "K7_PERFCTR3", > [0xc0010010 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_SYSCFG", > [0xc0010015 - x86_AMD_V_KVM_MSRs_offset] = "K7_HWCR", > [0xc001001a - x86_AMD_V_KVM_MSRs_offset] = "K8_TOP_MEM1", > [0xc001001b - x86_AMD_V_KVM_MSRs_offset] = "K7_CLK_CTL", > [0xc001001d - x86_AMD_V_KVM_MSRs_offset] = "K8_TOP_MEM2", > [0xc001001f - x86_AMD_V_KVM_MSRs_offset] = "AMD64_NB_CFG", > [0xc0010020 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_PATCH_LOADER", > [0xc0010041 - x86_AMD_V_KVM_MSRs_offset] = "K7_FID_VID_CTL", > [0xc0010042 - x86_AMD_V_KVM_MSRs_offset] = "K7_FID_VID_STATUS", > [0xc0010044 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_MC0_MASK", > [0xc0010055 - x86_AMD_V_KVM_MSRs_offset] = "K8_INT_PENDING_MSG", > [0xc0010058 - x86_AMD_V_KVM_MSRs_offset] = "FAM10H_MMIO_CONF_BASE", > [0xc0010062 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_CTL", > [0xc0010063 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_STATUS", > [0xc0010064 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PSTATE_DEF_BASE", > [0xc001007a - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_PWR_ACCUMULATOR", > [0xc001007b - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_MAX_PWR_ACCUMULATOR", > [0xc0010112 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_ADDR", > [0xc0010113 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_MASK", > [0xc0010114 - x86_AMD_V_KVM_MSRs_offset] = "VM_CR", > [0xc0010115 - x86_AMD_V_KVM_MSRs_offset] = "VM_IGNNE", > [0xc0010117 - x86_AMD_V_KVM_MSRs_offset] = "VM_HSAVE_PA", > [0xc001011e - x86_AMD_V_KVM_MSRs_offset] = "AMD64_VM_PAGE_FLUSH", > [0xc001011f - x86_AMD_V_KVM_MSRs_offset] = "AMD64_VIRT_SPEC_CTRL", > [0xc0010130 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_SEV_ES_GHCB", > [0xc0010131 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_SEV", > [0xc0010140 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_OSVW_ID_LENGTH", > [0xc0010141 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_OSVW_STATUS", > [0xc0010200 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PERF_CTL", > [0xc0010201 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PERF_CTR", > [0xc0010230 - x86_AMD_V_KVM_MSRs_offset] = "F16H_L2I_PERF_CTL", > [0xc0010231 - x86_AMD_V_KVM_MSRs_offset] = "F16H_L2I_PERF_CTR", > [0xc0010240 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTL", > [0xc0010241 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTR", > [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC", > [0xc0010299 - x86_AMD_V_KVM_MSRs_offset] = "AMD_RAPL_POWER_UNIT", > [0xc001029a - x86_AMD_V_KVM_MSRs_offset] = "AMD_CORE_ENERGY_STATUS", > [0xc001029b - x86_AMD_V_KVM_MSRs_offset] = "AMD_PKG_ENERGY_STATUS", > [0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL", > [0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN", > }; > ⬢[acme@toolbox perf]$ From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============6907691064775075520==" MIME-Version: 1.0 From: Rong Chen To: kbuild-all@lists.01.org Subject: Re: [tip:x86/cpu 4/4] Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 111< /* free ( 3*32+29) */ Date: Thu, 03 Jun 2021 15:43:59 +0800 Message-ID: <70606ff4-cdba-1c44-68c0-69e61c1bf65a@intel.com> In-Reply-To: List-Id: --===============6907691064775075520== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable On 6/2/21 11:35 PM, Arnaldo Carvalho de Melo wrote: > Em Wed, Jun 02, 2021 at 11:45:42AM +0200, Borislav Petkov escreveu: >> + acme. >> >> On Wed, Jun 02, 2021 at 05:41:53PM +0800, kernel test robot wrote: >>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86= /cpu >>> head: cbcddaa33d7e11a053cb80a4a635c023b4f8b906 >>> commit: cbcddaa33d7e11a053cb80a4a635c023b4f8b906 [4/4] perf/x86/rapl: U= se CPUID bit on AMD and Hygon parts >>> compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 >>> reproduce: >>> cd tools/perf && ./check-headers.sh >>> >>> If you fix the issue, kindly add following tag as appropriate >>> Reported-by: kernel test robot >>> >>> >>> perfheadercheck warnings: (new ones prefixed by >>) >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 87< #define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 87> /* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */ >>>>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures= .h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 1= 11< /* free ( 3*32+29) */ >>>>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures= .h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': 1= 11> #define X86_FEATURE_RAPL ( 3*32+29) /* AMD/Hygon RAPL interface */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 239> #define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 240> #define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempte= d function */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 295> #define X86_FEATURE_SGX1 (11*32+ 8) /* "" Basic SGX */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 296> #define X86_FEATURE_SGX2 (11*32+ 9) /* "" SGX Enclave Dynamic Memory= Management (EDMM) */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 343> #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 362> #define X86_FEATURE_BUS_LOCK_DETECT (16*32+24) /* Bus Lock detect */ >>> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatur= es.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h': = 383> #define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs o= f more than one type */ >>> >>> --- >>> 0-DAY CI Kernel Test Service, Intel Corporation >>> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org >> 0day folks, please make a note if you can, to send such cpufeatures.h >> header sync warnings to acme as he's verifying the feature bits modified >> before synching. >> >> Better yet, you can even ignore those altogether but I'm sure acme has a >> preference here. > Borislav, > > This is an attempt, suggested by PeterZ for us to try to > automate those updates, so what I was expecting wasn't a report that > something changed, as I notice it myself, but an attempt at checking if > the changes in these updates would entail changes in the tools build. > > Say, is there a script in tools/perf/trace/beauty/ that ends up > producing a different .c that then gets compiled/linked with tooling? Or > this is just a trivial change like happens from time to time, a typo > fix, some comments added, etc. > > Some examples of what those scripts do: > > =E2=AC=A2[acme(a)toolbox perf]$ tools/perf/trace/beauty/fadvise.sh > static const char *fadvise_advices[] =3D { > [0] =3D "NORMAL", > [1] =3D "RANDOM", > [2] =3D "SEQUENTIAL", > [3] =3D "WILLNEED", > [4] =3D "DONTNEED", > [5] =3D "NOREUSE", > }; > =E2=AC=A2[acme(a)toolbox perf]$ tools/perf/trace/beauty/socket.sh > static const char *socket_families[] =3D { > [0] =3D "UNSPEC", > [1] =3D "LOCAL", > [2] =3D "INET", > [3] =3D "AX25", > [4] =3D "IPX", > [5] =3D "APPLETALK", > [6] =3D "NETROM", > [7] =3D "BRIDGE", > [8] =3D "ATMPVC", > [9] =3D "X25", > [10] =3D "INET6", > [11] =3D "ROSE", > [12] =3D "DECnet", > [13] =3D "NETBEUI", > [14] =3D "SECURITY", > [15] =3D "KEY", > [16] =3D "NETLINK", > [17] =3D "PACKET", > [18] =3D "ASH", > [19] =3D "ECONET", > [20] =3D "ATMSVC", > [21] =3D "RDS", > [22] =3D "SNA", > [23] =3D "IRDA", > [24] =3D "PPPOX", > [25] =3D "WANPIPE", > [26] =3D "LLC", > [27] =3D "IB", > [28] =3D "MPLS", > [29] =3D "CAN", > [30] =3D "TIPC", > [31] =3D "BLUETOOTH", > [32] =3D "IUCV", > [33] =3D "RXRPC", > [34] =3D "ISDN", > [35] =3D "PHONET", > [36] =3D "IEEE802154", > [37] =3D "CAIF", > [38] =3D "ALG", > [39] =3D "NFC", > [40] =3D "VSOCK", > [41] =3D "KCM", > [42] =3D "QIPCRTR", > [43] =3D "SMC", > [44] =3D "XDP", > }; > =E2=AC=A2[acme(a)toolbox perf]$ > > Some of those files are used for building the tools, so that a > tarball generated from: > > =E2=AC=A2[acme(a)toolbox perf]$ make help | grep perf > perf-tar-src-pkg - Build perf-5.13.0-rc4.tar source tarball > perf-targz-src-pkg - Build perf-5.13.0-rc4.tar.gz source tarball > perf-tarbz2-src-pkg - Build perf-5.13.0-rc4.tar.bz2 source tarball > perf-tarxz-src-pkg - Build perf-5.13.0-rc4.tar.xz source tarball > =E2=AC=A2[acme(a)toolbox perf]$ > > will build in older systems where things added to the updated copy of > the kernel headers isn't present, so trying to update the file and then > rebuild perf, only warning me if it doesn't build would give me an early > warning about things that are breaking and that I should look sooner > rather than later. Hi Arnaldo, Thanks for the detailed explanation, I'm a little confused, do you mean we should both rebuild perf with the updated kernel headers and check the difference between headers by the scripts in = tools/perf/trace/beauty? Best Regards, Rong Chen > > Doing just the diff is not that useful :-) > > - Arnaldo > > One more output that is x86 specific and allows this to work: > > # perf trace -e msr:* --filter=3D"msr!=3DFS_BASE && msr !=3D IA32_= TSC_DEADLINE && msr !=3D 0x830 && msr !=3D 0x83f && msr !=3DIA32_SPEC_CTRL"= --filter-pids 3750 > 0.000 Timer/5033 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 0.009 Timer/5033 msr:write_msr(msr: LSTAR, val: -1398800368) > 0.010 Timer/5033 msr:write_msr(msr: TSC_AUX, val: 4) > 0.050 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 45.661 gnome-terminal/12595 msr:write_msr(msr: SYSCALL_MASK, val= : 292608) > 45.672 gnome-terminal/12595 msr:write_msr(msr: LSTAR, val: -1398= 800368) > 45.675 gnome-terminal/12595 msr:write_msr(msr: TSC_AUX, val: 3) > 54.852 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 130.508 Timer/4050 msr:write_msr(msr: SYSCALL_MASK, val: 292608) > 130.527 Timer/4050 msr:write_msr(msr: LSTAR, val: -1398800368) > 130.531 Timer/4050 msr:write_msr(msr: TSC_AUX, val: 3) > 140.924 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 164.738 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 603.578 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 620.809 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 690.115 JS Watchdog/4259 msr:write_msr(msr: SYSCALL_MASK, val: 29= 2608) > 690.136 JS Watchdog/4259 msr:write_msr(msr: LSTAR, val: -13988003= 68) > 690.141 JS Watchdog/4259 msr:write_msr(msr: TSC_AUX, val: 3) > 690.186 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > 759.016 :0/0 msr:read_msr(msr: IA32_TSC_ADJUST) > ^C[root(a)quaco ~]# > = > Or look at the first 3 write_msr events for that IA32_TSC_DEADLINE t= o learn why > it happens so often: > = > # perf trace --max-events=3D3 --max-stack=3D8 -e msr:* --filter=3D= "msr=3D=3DIA32_TSC_DEADLINE" --filter-pids 3750 > 0.000 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 192967325= 50862) > do_trace_write_msr ([kernel.k= allsyms]) > do_trace_write_msr ([kernel.k= allsyms]) > lapic_next_deadline ([kernel.= kallsyms]) > clockevents_program_event ([k= ernel.kallsyms]) > hrtimer_interrupt ([kernel.ka= llsyms]) > smp_apic_timer_interrupt ([ke= rnel.kallsyms]) > apic_timer_interrupt ([kernel= .kallsyms]) > cpuidle_enter_state ([kernel.= kallsyms]) > 32.646 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 192968001= 34158) > do_trace_write_msr ([kernel.k= allsyms]) > do_trace_write_msr ([kernel.k= allsyms]) > lapic_next_deadline ([kernel.= kallsyms]) > clockevents_program_event ([k= ernel.kallsyms]) > hrtimer_start_range_ns ([kern= el.kallsyms]) > tick_nohz_restart_sched_tick = ([kernel.kallsyms]) > tick_nohz_idle_exit ([kernel.= kallsyms]) > do_idle ([kernel.kallsyms]) > 32.802 :0/0 msr:write_msr(msr: IA32_TSC_DEADLINE, val: 192975074= 36922) > do_trace_write_msr ([kernel.k= allsyms]) > do_trace_write_msr ([kernel.k= allsyms]) > lapic_next_deadline ([kernel.= kallsyms]) > clockevents_program_event ([k= ernel.kallsyms]) > hrtimer_try_to_cancel ([kerne= l.kallsyms]) > hrtimer_cancel ([kernel.kalls= yms]) > tick_nohz_restart_sched_tick = ([kernel.kallsyms]) > tick_nohz_idle_exit ([kernel.= kallsyms]) > # > > > > =E2=AC=A2[acme(a)toolbox perf]$ tools/perf/trace/beauty/tracepoints/x86_m= sr.sh > static const char *x86_MSRs[] =3D { > [0x00000000] =3D "IA32_P5_MC_ADDR", > [0x00000001] =3D "IA32_P5_MC_TYPE", > [0x00000010] =3D "IA32_TSC", > [0x00000017] =3D "IA32_PLATFORM_ID", > [0x0000001b] =3D "IA32_APICBASE", > [0x00000020] =3D "KNC_PERFCTR0", > [0x00000021] =3D "KNC_PERFCTR1", > [0x00000028] =3D "KNC_EVNTSEL0", > [0x00000029] =3D "KNC_EVNTSEL1", > [0x0000002a] =3D "IA32_EBL_CR_POWERON", > [0x0000002c] =3D "EBC_FREQUENCY_ID", > [0x00000033] =3D "TEST_CTRL", > [0x00000034] =3D "SMI_COUNT", > [0x0000003a] =3D "IA32_FEAT_CTL", > [0x0000003b] =3D "IA32_TSC_ADJUST", > [0x00000040] =3D "LBR_CORE_FROM", > [0x00000048] =3D "IA32_SPEC_CTRL", > [0x00000049] =3D "IA32_PRED_CMD", > [0x0000004e] =3D "PPIN_CTL", > [0x0000004f] =3D "PPIN", > [0x00000060] =3D "LBR_CORE_TO", > [0x00000079] =3D "IA32_UCODE_WRITE", > [0x0000008b] =3D "AMD64_PATCH_LEVEL", > [0x0000008C] =3D "IA32_SGXLEPUBKEYHASH0", > [0x0000008D] =3D "IA32_SGXLEPUBKEYHASH1", > [0x0000008E] =3D "IA32_SGXLEPUBKEYHASH2", > [0x0000008F] =3D "IA32_SGXLEPUBKEYHASH3", > [0x0000009b] =3D "IA32_SMM_MONITOR_CTL", > [0x0000009e] =3D "IA32_SMBASE", > [0x000000c1] =3D "IA32_PERFCTR0", > [0x000000c2] =3D "IA32_PERFCTR1", > [0x000000cd] =3D "FSB_FREQ", > [0x000000ce] =3D "PLATFORM_INFO", > [0x000000cf] =3D "IA32_CORE_CAPS", > [0x000000e2] =3D "PKG_CST_CONFIG_CONTROL", > [0x000000e7] =3D "IA32_MPERF", > [0x000000e8] =3D "IA32_APERF", > [0x000000fe] =3D "MTRRcap", > [0x00000107] =3D "IDT_FCR1", > [0x00000108] =3D "IDT_FCR2", > [0x00000109] =3D "IDT_FCR3", > [0x0000010a] =3D "IA32_ARCH_CAPABILITIES", > [0x0000010b] =3D "IA32_FLUSH_CMD", > [0x0000010F] =3D "TSX_FORCE_ABORT", > [0x00000110] =3D "IDT_MCR0", > [0x00000111] =3D "IDT_MCR1", > [0x00000112] =3D "IDT_MCR2", > [0x00000113] =3D "IDT_MCR3", > [0x00000114] =3D "IDT_MCR4", > [0x00000115] =3D "IDT_MCR5", > [0x00000116] =3D "IDT_MCR6", > [0x00000117] =3D "IDT_MCR7", > [0x00000119] =3D "IA32_BBL_CR_CTL", > [0x0000011e] =3D "IA32_BBL_CR_CTL3", > [0x00000120] =3D "IDT_MCR_CTRL", > [0x00000122] =3D "IA32_TSX_CTRL", > [0x00000123] =3D "IA32_MCU_OPT_CTRL", > [0x00000140] =3D "MISC_FEATURES_ENABLES", > [0x00000174] =3D "IA32_SYSENTER_CS", > [0x00000175] =3D "IA32_SYSENTER_ESP", > [0x00000176] =3D "IA32_SYSENTER_EIP", > [0x00000179] =3D "IA32_MCG_CAP", > [0x0000017a] =3D "IA32_MCG_STATUS", > [0x0000017b] =3D "IA32_MCG_CTL", > [0x0000017f] =3D "ERROR_CONTROL", > [0x00000180] =3D "IA32_MCG_EAX", > [0x00000181] =3D "IA32_MCG_EBX", > [0x00000182] =3D "IA32_MCG_ECX", > [0x00000183] =3D "IA32_MCG_EDX", > [0x00000184] =3D "IA32_MCG_ESI", > [0x00000185] =3D "IA32_MCG_EDI", > [0x00000186] =3D "IA32_MCG_EBP", > [0x00000187] =3D "IA32_MCG_ESP", > [0x00000188] =3D "IA32_MCG_EFLAGS", > [0x00000189] =3D "IA32_MCG_EIP", > [0x0000018a] =3D "IA32_MCG_RESERVED", > [0x00000198] =3D "IA32_PERF_STATUS", > [0x00000199] =3D "IA32_PERF_CTL", > [0x0000019a] =3D "IA32_THERM_CONTROL", > [0x0000019b] =3D "IA32_THERM_INTERRUPT", > [0x0000019c] =3D "IA32_THERM_STATUS", > [0x0000019d] =3D "THERM2_CTL", > [0x000001a0] =3D "IA32_MISC_ENABLE", > [0x000001a2] =3D "IA32_TEMPERATURE_TARGET", > [0x000001a4] =3D "MISC_FEATURE_CONTROL", > [0x000001a6] =3D "OFFCORE_RSP_0", > [0x000001a7] =3D "OFFCORE_RSP_1", > [0x000001aa] =3D "MISC_PWR_MGMT", > [0x000001ad] =3D "TURBO_RATIO_LIMIT", > [0x000001ae] =3D "TURBO_RATIO_LIMIT1", > [0x000001af] =3D "TURBO_RATIO_LIMIT2", > [0x000001b0] =3D "IA32_ENERGY_PERF_BIAS", > [0x000001b1] =3D "IA32_PACKAGE_THERM_STATUS", > [0x000001b2] =3D "IA32_PACKAGE_THERM_INTERRUPT", > [0x000001c8] =3D "LBR_SELECT", > [0x000001c9] =3D "LBR_TOS", > [0x000001d9] =3D "IA32_DEBUGCTLMSR", > [0x000001db] =3D "IA32_LASTBRANCHFROMIP", > [0x000001dc] =3D "IA32_LASTBRANCHTOIP", > [0x000001dd] =3D "IA32_LASTINTFROMIP", > [0x000001de] =3D "IA32_LASTINTTOIP", > [0x000001fc] =3D "IA32_POWER_CTL", > [0x00000250] =3D "MTRRfix64K_00000", > [0x00000258] =3D "MTRRfix16K_80000", > [0x00000259] =3D "MTRRfix16K_A0000", > [0x00000268] =3D "MTRRfix4K_C0000", > [0x00000269] =3D "MTRRfix4K_C8000", > [0x0000026a] =3D "MTRRfix4K_D0000", > [0x0000026b] =3D "MTRRfix4K_D8000", > [0x0000026c] =3D "MTRRfix4K_E0000", > [0x0000026d] =3D "MTRRfix4K_E8000", > [0x0000026e] =3D "MTRRfix4K_F0000", > [0x0000026f] =3D "MTRRfix4K_F8000", > [0x00000277] =3D "IA32_CR_PAT", > [0x00000280] =3D "IA32_MC0_CTL2", > [0x000002ff] =3D "MTRRdefType", > [0x00000309] =3D "CORE_PERF_FIXED_CTR0", > [0x0000030a] =3D "CORE_PERF_FIXED_CTR1", > [0x0000030b] =3D "CORE_PERF_FIXED_CTR2", > [0x0000030c] =3D "CORE_PERF_FIXED_CTR3", > [0x00000329] =3D "PERF_METRICS", > [0x00000345] =3D "IA32_PERF_CAPABILITIES", > [0x0000038d] =3D "CORE_PERF_FIXED_CTR_CTRL", > [0x0000038e] =3D "CORE_PERF_GLOBAL_STATUS", > [0x0000038f] =3D "CORE_PERF_GLOBAL_CTRL", > [0x00000390] =3D "CORE_PERF_GLOBAL_OVF_CTRL", > [0x000003f1] =3D "IA32_PEBS_ENABLE", > [0x000003f2] =3D "PEBS_DATA_CFG", > [0x000003f6] =3D "PEBS_LD_LAT_THRESHOLD", > [0x000003f7] =3D "PEBS_FRONTEND", > [0x000003f8] =3D "PKG_C3_RESIDENCY", > [0x000003f9] =3D "PKG_C6_RESIDENCY", > [0x000003fa] =3D "PKG_C7_RESIDENCY", > [0x000003fc] =3D "CORE_C3_RESIDENCY", > [0x000003fd] =3D "CORE_C6_RESIDENCY", > [0x000003fe] =3D "CORE_C7_RESIDENCY", > [0x000003ff] =3D "KNL_CORE_C6_RESIDENCY", > [0x00000400] =3D "IA32_MC0_CTL", > [0x00000401] =3D "IA32_MC0_STATUS", > [0x00000402] =3D "IA32_MC0_ADDR", > [0x00000403] =3D "IA32_MC0_MISC", > [0x00000480] =3D "IA32_VMX_BASIC", > [0x00000481] =3D "IA32_VMX_PINBASED_CTLS", > [0x00000482] =3D "IA32_VMX_PROCBASED_CTLS", > [0x00000483] =3D "IA32_VMX_EXIT_CTLS", > [0x00000484] =3D "IA32_VMX_ENTRY_CTLS", > [0x00000485] =3D "IA32_VMX_MISC", > [0x00000486] =3D "IA32_VMX_CR0_FIXED0", > [0x00000487] =3D "IA32_VMX_CR0_FIXED1", > [0x00000488] =3D "IA32_VMX_CR4_FIXED0", > [0x00000489] =3D "IA32_VMX_CR4_FIXED1", > [0x0000048a] =3D "IA32_VMX_VMCS_ENUM", > [0x0000048b] =3D "IA32_VMX_PROCBASED_CTLS2", > [0x0000048c] =3D "IA32_VMX_EPT_VPID_CAP", > [0x0000048d] =3D "IA32_VMX_TRUE_PINBASED_CTLS", > [0x0000048e] =3D "IA32_VMX_TRUE_PROCBASED_CTLS", > [0x0000048f] =3D "IA32_VMX_TRUE_EXIT_CTLS", > [0x00000490] =3D "IA32_VMX_TRUE_ENTRY_CTLS", > [0x00000491] =3D "IA32_VMX_VMFUNC", > [0x000004c1] =3D "IA32_PMC0", > [0x000004d0] =3D "IA32_MCG_EXT_CTL", > [0x00000560] =3D "IA32_RTIT_OUTPUT_BASE", > [0x00000561] =3D "IA32_RTIT_OUTPUT_MASK", > [0x00000570] =3D "IA32_RTIT_CTL", > [0x00000571] =3D "IA32_RTIT_STATUS", > [0x00000572] =3D "IA32_RTIT_CR3_MATCH", > [0x00000580] =3D "IA32_RTIT_ADDR0_A", > [0x00000581] =3D "IA32_RTIT_ADDR0_B", > [0x00000582] =3D "IA32_RTIT_ADDR1_A", > [0x00000583] =3D "IA32_RTIT_ADDR1_B", > [0x00000584] =3D "IA32_RTIT_ADDR2_A", > [0x00000585] =3D "IA32_RTIT_ADDR2_B", > [0x00000586] =3D "IA32_RTIT_ADDR3_A", > [0x00000587] =3D "IA32_RTIT_ADDR3_B", > [0x00000600] =3D "IA32_DS_AREA", > [0x00000606] =3D "RAPL_POWER_UNIT", > [0x0000060a] =3D "PKGC3_IRTL", > [0x0000060b] =3D "PKGC6_IRTL", > [0x0000060c] =3D "PKGC7_IRTL", > [0x0000060d] =3D "PKG_C2_RESIDENCY", > [0x00000610] =3D "PKG_POWER_LIMIT", > [0x00000611] =3D "PKG_ENERGY_STATUS", > [0x00000613] =3D "PKG_PERF_STATUS", > [0x00000614] =3D "PKG_POWER_INFO", > [0x00000618] =3D "DRAM_POWER_LIMIT", > [0x00000619] =3D "DRAM_ENERGY_STATUS", > [0x0000061b] =3D "DRAM_PERF_STATUS", > [0x0000061c] =3D "DRAM_POWER_INFO", > [0x00000630] =3D "PKG_C8_RESIDENCY", > [0x00000631] =3D "PKG_C9_RESIDENCY", > [0x00000632] =3D "PKG_C10_RESIDENCY", > [0x00000633] =3D "PKGC8_IRTL", > [0x00000634] =3D "PKGC9_IRTL", > [0x00000635] =3D "PKGC10_IRTL", > [0x00000638] =3D "PP0_POWER_LIMIT", > [0x00000639] =3D "PP0_ENERGY_STATUS", > [0x0000063a] =3D "PP0_POLICY", > [0x0000063b] =3D "PP0_PERF_STATUS", > [0x00000640] =3D "PP1_POWER_LIMIT", > [0x00000641] =3D "PP1_ENERGY_STATUS", > [0x00000642] =3D "PP1_POLICY", > [0x00000648] =3D "CONFIG_TDP_NOMINAL", > [0x00000649] =3D "CONFIG_TDP_LEVEL_1", > [0x0000064A] =3D "CONFIG_TDP_LEVEL_2", > [0x0000064B] =3D "CONFIG_TDP_CONTROL", > [0x0000064C] =3D "TURBO_ACTIVATION_RATIO", > [0x0000064D] =3D "PLATFORM_ENERGY_STATUS", > [0x0000064e] =3D "PPERF", > [0x0000064f] =3D "PERF_LIMIT_REASONS", > [0x00000658] =3D "PKG_WEIGHTED_CORE_C0_RES", > [0x00000659] =3D "PKG_ANY_CORE_C0_RES", > [0x0000065A] =3D "PKG_ANY_GFXE_C0_RES", > [0x0000065B] =3D "PKG_BOTH_CORE_GFXE_C0_RES", > [0x00000660] =3D "CORE_C1_RES", > [0x00000664] =3D "MODULE_C6_RES_MS", > [0x00000668] =3D "CC6_DEMOTION_POLICY_CONFIG", > [0x00000669] =3D "MC6_DEMOTION_POLICY_CONFIG", > [0x00000680] =3D "LBR_NHM_FROM", > [0x00000690] =3D "CORE_PERF_LIMIT_REASONS", > [0x000006B0] =3D "GFX_PERF_LIMIT_REASONS", > [0x000006B1] =3D "RING_PERF_LIMIT_REASONS", > [0x000006c0] =3D "LBR_NHM_TO", > [0x00000770] =3D "PM_ENABLE", > [0x00000771] =3D "HWP_CAPABILITIES", > [0x00000772] =3D "HWP_REQUEST_PKG", > [0x00000773] =3D "HWP_INTERRUPT", > [0x00000774] =3D "HWP_REQUEST", > [0x00000777] =3D "HWP_STATUS", > [0x00000d90] =3D "IA32_BNDCFGS", > [0x00000d93] =3D "IA32_PASID", > [0x00000da0] =3D "IA32_XSS", > [0x00000dc0] =3D "LBR_INFO_0", > [0x00000ffc] =3D "IA32_BNDCFGS_RSVD", > }; > > #define x86_64_specific_MSRs_offset 0xc0000080 > static const char *x86_64_specific_MSRs[] =3D { > [0xc0000080 - x86_64_specific_MSRs_offset] =3D "EFER", > [0xc0000081 - x86_64_specific_MSRs_offset] =3D "STAR", > [0xc0000082 - x86_64_specific_MSRs_offset] =3D "LSTAR", > [0xc0000083 - x86_64_specific_MSRs_offset] =3D "CSTAR", > [0xc0000084 - x86_64_specific_MSRs_offset] =3D "SYSCALL_MASK", > [0xc0000085 - x86_64_specific_MSRs_offset] =3D "K6_UWCCR", > [0xc0000086 - x86_64_specific_MSRs_offset] =3D "K6_EPMR", > [0xc0000087 - x86_64_specific_MSRs_offset] =3D "K6_PSOR", > [0xc0000088 - x86_64_specific_MSRs_offset] =3D "K6_PFIR", > [0xc00000e9 - x86_64_specific_MSRs_offset] =3D "F17H_IRPERF", > [0xc0000100 - x86_64_specific_MSRs_offset] =3D "FS_BASE", > [0xc0000101 - x86_64_specific_MSRs_offset] =3D "GS_BASE", > [0xc0000102 - x86_64_specific_MSRs_offset] =3D "KERNEL_GS_BASE", > [0xc0000103 - x86_64_specific_MSRs_offset] =3D "TSC_AUX", > [0xc0000104 - x86_64_specific_MSRs_offset] =3D "AMD64_TSC_RATIO", > }; > > #define x86_AMD_V_KVM_MSRs_offset 0xc0010000 > static const char *x86_AMD_V_KVM_MSRs[] =3D { > [0xc0010000 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_EVNTSEL0", > [0xc0010001 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_EVNTSEL1", > [0xc0010002 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_EVNTSEL2", > [0xc0010003 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_EVNTSEL3", > [0xc0010004 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_PERFCTR0", > [0xc0010005 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_PERFCTR1", > [0xc0010006 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_PERFCTR2", > [0xc0010007 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_PERFCTR3", > [0xc0010010 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_SYSCFG", > [0xc0010015 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_HWCR", > [0xc001001a - x86_AMD_V_KVM_MSRs_offset] =3D "K8_TOP_MEM1", > [0xc001001b - x86_AMD_V_KVM_MSRs_offset] =3D "K7_CLK_CTL", > [0xc001001d - x86_AMD_V_KVM_MSRs_offset] =3D "K8_TOP_MEM2", > [0xc001001f - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_NB_CFG", > [0xc0010020 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_PATCH_LOADER", > [0xc0010041 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_FID_VID_CTL", > [0xc0010042 - x86_AMD_V_KVM_MSRs_offset] =3D "K7_FID_VID_STATUS", > [0xc0010044 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_MC0_MASK", > [0xc0010055 - x86_AMD_V_KVM_MSRs_offset] =3D "K8_INT_PENDING_MSG", > [0xc0010058 - x86_AMD_V_KVM_MSRs_offset] =3D "FAM10H_MMIO_CONF_BASE", > [0xc0010062 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PERF_CTL", > [0xc0010063 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PERF_STATUS", > [0xc0010064 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PSTATE_DEF_BASE", > [0xc001007a - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_CU_PWR_ACCUMULATOR", > [0xc001007b - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_CU_MAX_PWR_ACCUMULATO= R", > [0xc0010112 - x86_AMD_V_KVM_MSRs_offset] =3D "K8_TSEG_ADDR", > [0xc0010113 - x86_AMD_V_KVM_MSRs_offset] =3D "K8_TSEG_MASK", > [0xc0010114 - x86_AMD_V_KVM_MSRs_offset] =3D "VM_CR", > [0xc0010115 - x86_AMD_V_KVM_MSRs_offset] =3D "VM_IGNNE", > [0xc0010117 - x86_AMD_V_KVM_MSRs_offset] =3D "VM_HSAVE_PA", > [0xc001011e - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_VM_PAGE_FLUSH", > [0xc001011f - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_VIRT_SPEC_CTRL", > [0xc0010130 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_SEV_ES_GHCB", > [0xc0010131 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_SEV", > [0xc0010140 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_OSVW_ID_LENGTH", > [0xc0010141 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD64_OSVW_STATUS", > [0xc0010200 - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_PERF_CTL", > [0xc0010201 - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_PERF_CTR", > [0xc0010230 - x86_AMD_V_KVM_MSRs_offset] =3D "F16H_L2I_PERF_CTL", > [0xc0010231 - x86_AMD_V_KVM_MSRs_offset] =3D "F16H_L2I_PERF_CTR", > [0xc0010240 - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_NB_PERF_CTL", > [0xc0010241 - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_NB_PERF_CTR", > [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] =3D "F15H_PTSC", > [0xc0010299 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_RAPL_POWER_UNIT", > [0xc001029a - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_CORE_ENERGY_STATUS", > [0xc001029b - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PKG_ENERGY_STATUS", > [0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PPIN_CTL", > [0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] =3D "AMD_PPIN", > }; > =E2=AC=A2[acme(a)toolbox perf]$ --===============6907691064775075520==--