* [RFC PATCH 0/8] RISCV risu porting
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
When I test RISCV vector extension, many folks advice risu. Here is a
very simple port only support RV64I, RV64F, RV64M.
It's some difficult when I try to support RV32, because it's very
similiar to RV64, so I can't make two .risu files like arm.risu and
aarch64.risu.
Any idea are welcomed.
LIU Zhiwei (8):
riscv: Add RV64I instructions description
riscv: Generate payload scripts
riscv: Define riscv struct reginfo
riscv: Implement payload load interfaces
riscv: Add standard test case
riscv: Add configure script
riscv: Add RV64M instructions description
riscv: Add RV64F instructions description
configure | 4 +-
riscv64.risu | 262 +++++++++++++++++++++
risu_reginfo_riscv64.c | 134 +++++++++++
risu_reginfo_riscv64.h | 29 +++
risu_riscv64.c | 47 ++++
risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++
test_riscv64.s | 85 +++++++
7 files changed, 1061 insertions(+), 1 deletion(-)
create mode 100644 riscv64.risu
create mode 100644 risu_reginfo_riscv64.c
create mode 100644 risu_reginfo_riscv64.h
create mode 100644 risu_riscv64.c
create mode 100644 risugen_riscv.pm
create mode 100644 test_riscv64.s
--
2.23.0
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH 0/8] RISCV risu porting
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
When I test RISCV vector extension, many folks advice risu. Here is a
very simple port only support RV64I, RV64F, RV64M.
It's some difficult when I try to support RV32, because it's very
similiar to RV64, so I can't make two .risu files like arm.risu and
aarch64.risu.
Any idea are welcomed.
LIU Zhiwei (8):
riscv: Add RV64I instructions description
riscv: Generate payload scripts
riscv: Define riscv struct reginfo
riscv: Implement payload load interfaces
riscv: Add standard test case
riscv: Add configure script
riscv: Add RV64M instructions description
riscv: Add RV64F instructions description
configure | 4 +-
riscv64.risu | 262 +++++++++++++++++++++
risu_reginfo_riscv64.c | 134 +++++++++++
risu_reginfo_riscv64.h | 29 +++
risu_riscv64.c | 47 ++++
risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++
test_riscv64.s | 85 +++++++
7 files changed, 1061 insertions(+), 1 deletion(-)
create mode 100644 riscv64.risu
create mode 100644 risu_reginfo_riscv64.c
create mode 100644 risu_reginfo_riscv64.h
create mode 100644 risu_riscv64.c
create mode 100644 risugen_riscv.pm
create mode 100644 test_riscv64.s
--
2.23.0
^ permalink raw reply [flat|nested] 56+ messages in thread
* [RFC PATCH 1/8] riscv: Add RV64I instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 riscv64.risu
diff --git a/riscv64.risu b/riscv64.risu
new file mode 100644
index 0000000..98141ab
--- /dev/null
+++ b/riscv64.risu
@@ -0,0 +1,141 @@
+# Input file for risugen defining RISC-V instructions
+.mode riscv
+@RV64I
+
+# x2 stack pointer, x3 global pointer, x4 thread pointer
+# These registers should be reserved for signal handler.
+
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+AUIPC RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+# Limit to current implementation, the base address register will be overide
+LB RISCV imm:12 rs1:5 000 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LH RISCV imm:12 rs1:5 001 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LW RISCV imm:12 rs1:5 010 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LD RISCV imm:12 rs1:5 011 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 1/8] riscv: Add RV64I instructions description
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 riscv64.risu
diff --git a/riscv64.risu b/riscv64.risu
new file mode 100644
index 0000000..98141ab
--- /dev/null
+++ b/riscv64.risu
@@ -0,0 +1,141 @@
+# Input file for risugen defining RISC-V instructions
+.mode riscv
+@RV64I
+
+# x2 stack pointer, x3 global pointer, x4 thread pointer
+# These registers should be reserved for signal handler.
+
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+AUIPC RISCV imm:20 rd:5 0110111 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+# Limit to current implementation, the base address register will be overide
+LB RISCV imm:12 rs1:5 000 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LH RISCV imm:12 rs1:5 001 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LW RISCV imm:12 rs1:5 010 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+LD RISCV imm:12 rs1:5 011 rd:5 0000011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 0 && $rs1 != 2 && $rs1 != 3 && $rs1 != 4 } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 2/8] riscv: Generate payload scripts
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 risugen_riscv.pm
diff --git a/risugen_riscv.pm b/risugen_riscv.pm
new file mode 100644
index 0000000..092c246
--- /dev/null
+++ b/risugen_riscv.pm
@@ -0,0 +1,501 @@
+#!/usr/bin/perl -w
+###############################################################################
+# All rights reserved. This program and the accompanying materials
+# are made available under the terms of the Eclipse Public License v1.0
+# which accompanies this distribution, and is available at
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Contributors:
+# LIU Zhiwei (PingTouGe) - RISC-V implementation
+# based on Peter Maydell (Linaro) - initial implementation
+###############################################################################
+
+# risugen -- generate a test binary file for use with risu
+# See 'risugen --help' for usage information.
+package risugen_riscv;
+
+use strict;
+use warnings;
+
+use risugen_common;
+
+require Exporter;
+
+our @ISA = qw(Exporter);
+our @EXPORT = qw(write_test_code);
+
+my $periodic_reg_random = 1;
+
+#
+# Maximum alignment restriction permitted for a memory op.
+my $MAXALIGN = 64;
+sub ctz($)
+{
+ my ($imm) = @_;
+ my $cnt = 0;
+
+ if ($imm == 0) {
+ return 0;
+ }
+ while (($imm & 1) == 0) {
+ $cnt++;
+ $imm = $imm >> 1;
+ }
+ return $cnt;
+}
+
+sub decode_li($)
+{
+ my ($imm) = @_;
+ my $cnt = 0;
+ my $idx = 0;
+ my $part = 0;
+ my $next = 0;
+ my %result;
+
+ $next = $imm;
+ # only one lui can not hold
+ while ((($next >> 12) != sextract(($next >> 12) & 0xfffff, 20)) ||
+ (($next & 0xfff) != 0)) {
+ # at the first time, just eat the least 12 bits
+ if ($idx == 0) {
+ $part = sextract($imm & 0xfff, 12);
+ $result{"first"} = $part;
+ } else {
+ $imm = $imm - $part; # clear the part before it
+ $cnt = ctz($imm); # add a shift
+ $imm >>= $cnt;
+ $part = sextract($imm & 0xfff, 12);
+ $result{"mid"}{$idx}{"part"} = $part;
+ $result{"mid"}{$idx}{"cnt"} = $cnt;
+ $next = $imm - $part;
+ }
+ $idx++;
+ }
+ # output a lui
+ $result{"lui"} = sextract(($next >> 12) & 0xfffff, 20);
+ return %result;
+}
+
+# li is implements as Myraid sequences, just the common way here
+sub write_mov_ri($$)
+{
+ my ($rd, $imm) = @_;
+
+ # sequence of li rd, 0x1234567887654321
+ #
+ # 0: 002471b7 lui rd,0x247
+ # 4: 8ad1819b addiw rd,rd,-1875
+ # 8: 00c19193 slli rd,rd,0xc
+ # c: f1118193 addi rd,rd,-239 # 0x246f11
+ # 10: 00d19193 slli rd,rd,0xd
+ # 14: d9518193 addi rd,rd,-619
+ # 18: 00e19193 slli rd,rd,0xe
+ # 1c: 32118193 addi rd,rd,801
+ my %result = decode_li($imm);
+
+ my $len = keys %{$result{"mid"}};
+ my $i = 0;
+
+ # output the last lui
+ insn32(0x00000037 | $rd << 7 | $result{"lui"} << 12);
+ # output the sequence of slli and addi
+ foreach my $key (reverse sort keys %{$result{"mid"}}) {
+ $i++;
+ if ($i == 1) {
+ # output the last addiw
+ insn32(0x0000001b | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"part"} << 20);
+ # slli rd, rd, $result{"mid"}{$key}{"part"}
+ insn32(0x00001013 | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"cnt"} << 20);
+ } else {
+ insn32(0x00000013 | $rd << 7 | $rd << 15 |
+ ($result{"mid"}{$key}{"part"} & 0xfff) << 20);
+ # slli rd, rd, $result{"mid"}{$key}{"part"}
+ insn32(0x00001013 | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"cnt"} << 20);
+ }
+ }
+ # addi rd, rd, $result{"first"}
+ insn32(0x00000013 | $rd << 7 | $rd << 15 | ($imm & 0xfff) << 20);
+}
+
+sub write_mov_rr($$)
+{
+ my ($rd, $rs1) = @_;
+
+ # addi $rd, $rs1, 0
+ insn32(0x00000013 | $rd << 7 | $rs1 << 15);
+}
+
+sub write_sub_rrr($$$)
+{
+ my ($rd, $rs1, $rs2) = @_;
+
+ # sub $rd, $rs1, $rs2
+ insn32(0x40000033 |$rd << 7 | $rs1 << 15 | $rs2 << 20);
+}
+
+my $OP_COMPARE = 0; # compare registers
+my $OP_TESTEND = 1; # end of test, stop
+my $OP_SETMEMBLOCK = 2; # r0 is address of memory block (8192 bytes)
+my $OP_GETMEMBLOCK = 3; # add the address of memory block to r0
+my $OP_COMPAREMEM = 4; # compare memory block
+
+# write random fp value of passed precision (1=single, 2=double)
+sub write_random_fpreg_var($)
+{
+ my ($precision) = @_;
+ my $randomize_low = 0;
+
+ if ($precision != 1 && $precision != 2) {
+ die "write_random_fpreg: invalid precision.\n";
+ }
+
+ my ($low, $high);
+ my $r = rand(100);
+ if ($r < 5) {
+ # +-0 (5%)
+ $low = $high = 0;
+ $high |= 0x80000000 if (rand() < 0.5);
+ } elsif ($r < 10) {
+ # NaN (5%)
+ # (plus a tiny chance of generating +-Inf)
+ $randomize_low = 1;
+ $high = rand(0xffffffff) | 0x7ff00000;
+ } elsif ($r < 15) {
+ # Infinity (5%)
+ $low = 0;
+ $high = 0x7ff00000;
+ $high |= 0x80000000 if (rand() < 0.5);
+ } elsif ($r < 30) {
+ # Denormalized number (15%)
+ # (plus tiny chance of +-0)
+ $randomize_low = 1;
+ $high = rand(0xffffffff) & ~0x7ff00000;
+ } else {
+ # Normalized number (70%)
+ # (plus a small chance of the other cases)
+ $randomize_low = 1;
+ $high = rand(0xffffffff);
+ }
+
+ for (my $i = 1; $i < $precision; $i++) {
+ if ($randomize_low) {
+ $low = rand(0xffffffff);
+ }
+ insn32($low);
+ }
+ insn32($high);
+}
+
+sub write_random_riscv64_fpdata()
+{
+ # load floating point registers
+ my $align = 16;
+ my $datalen = 32 * 8 + $align;
+ write_pc_adr(10, (4 * 4) + ($align - 1)); # insn 1
+ write_align_reg(10, $align); # insn 2
+ write_jump_fwd($datalen + 4); # insn 3
+
+ # align safety
+ for (my $i = 0; $i < ($align / 4); $i++) {
+ insn32(rand(0xffffffff));
+ }
+
+ # Todo: As the x10 aligned, it won't be the base address of
+ # the interesting numbers.
+ for (my $rt = 0; $rt <= 31; $rt++) {
+ write_random_fpreg_var(2); # double
+ }
+
+ for (my ($rt, $imm) = (0, 0); $rt < 32; $rt++) {
+ # fld rt, x10, imm
+ insn32(0x00003007 | ($imm << 20) | (10 << 15) | ($rt << 7));
+ $imm += 8;
+ }
+}
+
+sub write_random_register_data($)
+{
+ my ($fp_enabled) = @_;
+
+ if ($fp_enabled) {
+ # load floating point
+ write_random_riscv64_fpdata();
+ }
+
+ # general purpose registers
+ for (my $i = 1; $i < 32; $i++) {
+ if ($i != 2 && $i != 3 && $i!= 4) {
+ # TODO full 64 bit pattern instead of 32
+ write_mov_ri($i, rand(0xffffffff));
+ }
+ }
+ write_risuop($OP_COMPARE);
+}
+
+# put PC + offset into a register.
+# this must emit an instruction of 8 bytes.
+sub write_pc_adr($$)
+{
+ my ($rd, $imm) = @_;
+
+ # auipc rd, 0
+ # addi rd, rd, imm
+ insn32(0x00000017 | $rd << 7);
+ insn32(0x00000013 | $imm << 20 | $rd << 15 | $rd << 7);
+}
+
+# clear bits in register to satisfy alignment.
+# Must use exactly 4 instruction-bytes
+sub write_align_reg($$)
+{
+ my ($rd, $align) = @_;
+ my $imm = (-$align) & 0xfff;
+ die "bad alignment!" if ($align < 2);
+
+ # andi rd, rd, ~(align - 1)
+ insn32(0x00007013 | $imm << 20 | $rd << 15 | $rd << 7);
+}
+
+# jump ahead of n bytes starting from next instruction
+sub write_jump_fwd($)
+{
+ my ($len) = @_;
+
+ # 31 30 21 20 19 12 11 7 6 0
+ # imm[20] imm[10:1] imm[11] imm[19:12] rd opcode
+ # 1 10 1 8 5 7
+ # offset[20:1] dest JAL
+ my ($imm20, $imm1, $imm11, $imm12) = (($len & 0x100000) >> 20, ($len & 0x7fe) >> 1,
+ ($len & 0x800) >> 11, ($len & 0xff000) >> 12);
+
+ # jal x0, len
+ insn32(0x0000006f | $imm20 << 31 | $imm1 << 21 | $imm11 << 20 |
+ $imm12 << 12);
+}
+
+sub write_memblock_setup()
+{
+ # Write code which sets up the memory block for loads and stores.
+ # We set r0 to point to a block of 16K length
+ # of random data, aligned to the maximum desired alignment.
+
+ my $align = $MAXALIGN;
+ my $datalen = 16384 + $align;
+ if (($align > 255) || !is_pow_of_2($align) || $align < 4) {
+ die "bad alignment!";
+ }
+
+ # set x10 to (datablock + (align-1)) & ~(align-1)
+ # datablock is at PC + (4 * 5 instructions) = PC + 20
+ write_pc_adr(10, (4 * 5) + ($align - 1)); # insn 1
+ write_align_reg(10, $align); # insn 2
+ write_risuop($OP_SETMEMBLOCK); # insn 3
+ write_jump_fwd($datalen + 4); # insn 4
+
+ for (my $i = 0; $i < $datalen / 4; $i++) {
+ insn32(rand(0xffffffff));
+ }
+ # next:
+}
+
+# Functions used in memory blocks to handle addressing modes.
+# These all have the same basic API: they get called with parameters
+# corresponding to the interesting fields of the instruction,
+# and should generate code to set up the base register to be
+# valid. They must return the register number of the base register.
+# The last (array) parameter lists the registers which are trashed
+# by the instruction (ie which are the targets of the load).
+# This is used to avoid problems when the base reg is a load target.
+
+# Global used to communicate between align(x) and reg() etc.
+my $alignment_restriction;
+
+sub align($)
+{
+ my ($a) = @_;
+ if (!is_pow_of_2($a) || ($a < 0) || ($a > $MAXALIGN)) {
+ die "bad align() value $a\n";
+ }
+ $alignment_restriction = $a;
+}
+
+sub write_get_offset()
+{
+ # Emit code to get a random offset within the memory block, of the
+ # right alignment, into r0
+ # We require the offset to not be within 256 bytes of either
+ # end, to (more than) allow for the worst case data transfer, which is
+ # 16 * 64 bit regs
+ my $offset = (rand(16384 - 8192) + 4096) & ~($alignment_restriction - 1);
+ write_mov_ri(10, $offset);
+ write_risuop($OP_GETMEMBLOCK);
+}
+
+sub reg($@)
+{
+ my ($base, @trashed) = @_;
+ write_get_offset();
+ # Now x10 is the address we want to do the access to,
+ # so just move it into the basereg
+ if ($base != 10) {
+ write_mov_rr($base, 10);
+ write_mov_ri(10, 0);
+ }
+ if (grep $_ == $base, @trashed) {
+ return -1;
+ }
+ return $base;
+}
+
+sub reg_plus_imm($$@)
+{
+ # Handle reg + immediate addressing mode
+ my ($base, $imm, @trashed) = @_;
+ if ($imm == 0) {
+ return reg($base, @trashed);
+ }
+
+ write_get_offset();
+ # Now x10 is the address we want to do the access to,
+ # so set the basereg by doing the inverse of the
+ # addressing mode calculation, ie base = x10 - imm
+ # We could do this more cleverly with a sub immediate.
+ if ($base != 10) {
+ write_mov_ri($base, $imm);
+ write_sub_rrr($base, 10, $base);
+ # Clear x10 to avoid register compare mismatches
+ # when the memory block location differs between machines.
+ write_mov_ri(10, 0);
+ } else {
+ # We borrow x11 as a temporary (not a problem
+ # as long as we don't leave anything in a register
+ # which depends on the location of the memory block)
+ write_mov_ri(11, $imm);
+ write_sub_rrr($base, 10, 11);
+ }
+ if (grep $_ == $base, @trashed) {
+ return -1;
+ }
+ return $base;
+}
+
+sub gen_one_insn($)
+{
+ # Given an instruction-details array, generate an instruction
+ my $constraintfailures = 0;
+
+ INSN: while(1) {
+ my ($rec) = @_;
+ my $insn = int(rand(0xffffffff));
+ my $insnname = $rec->{name};
+ my $insnwidth = $rec->{width};
+ my $fixedbits = $rec->{fixedbits};
+ my $fixedbitmask = $rec->{fixedbitmask};
+ my $constraint = $rec->{blocks}{"constraints"};
+ my $memblock = $rec->{blocks}{"memory"};
+
+ $insn &= ~$fixedbitmask;
+ $insn |= $fixedbits;
+
+ if (defined $constraint) {
+ # user-specified constraint: evaluate in an environment
+ # with variables set corresponding to the variable fields.
+ my $v = eval_with_fields($insnname, $insn, $rec, "constraints", $constraint);
+ if (!$v) {
+ $constraintfailures++;
+ if ($constraintfailures > 10000) {
+ print "10000 consecutive constraint failures for $insnname constraints string:\n$constraint\n";
+ exit (1);
+ }
+ next INSN;
+ }
+ }
+
+ # OK, we got a good one
+ $constraintfailures = 0;
+
+ my $basereg;
+
+ if (defined $memblock) {
+ # This is a load or store. We simply evaluate the block,
+ # which is expected to be a call to a function which emits
+ # the code to set up the base register and returns the
+ # number of the base register.
+ # we use 16 for riscv64, although often unnecessary and overkill.
+ align(16);
+ $basereg = eval_with_fields($insnname, $insn, $rec, "memory", $memblock);
+ }
+
+ insn32($insn);
+
+ if (defined $memblock) {
+ # Clean up following a memory access instruction:
+ # we need to turn the (possibly written-back) basereg
+ # into an offset from the base of the memory block,
+ # to avoid making register values depend on memory layout.
+ # $basereg -1 means the basereg was a target of a load
+ # (and so it doesn't contain a memory address after the op)
+ if ($basereg != -1) {
+ write_mov_ri($basereg, 0);
+ }
+ }
+ return;
+ }
+}
+
+sub write_risuop($)
+{
+ # instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED
+ my ($op) = @_;
+ insn32(0x0000006b | $op << 8);
+}
+
+sub write_test_code($)
+{
+ my ($params) = @_;
+
+ my $numinsns = $params->{ 'numinsns' };
+ my $fp_enabled = $params->{ 'fp_enabled' };
+ my $outfile = $params->{ 'outfile' };
+
+ my %insn_details = %{ $params->{ 'details' } };
+ my @keys = @{ $params->{ 'keys' } };
+
+ print "Enter write code", "\n";
+ open_bin($outfile);
+
+ # TODO better random number generator?
+ srand(0);
+
+ print "Generating code using patterns: @keys...\n";
+ progress_start(78, $numinsns);
+
+ if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) {
+ write_memblock_setup();
+ }
+
+ # memblock setup doesn't clean its registers, so this must come afterwards.
+ write_random_register_data($fp_enabled);
+
+ for my $i (1..$numinsns) {
+ my $insn_enc = $keys[int rand (@keys)];
+ #dump_insn_details($insn_enc, $insn_details{$insn_enc});
+ gen_one_insn($insn_details{$insn_enc});
+ write_risuop($OP_COMPARE);
+ # Rewrite the registers periodically. This avoids the tendency
+ # for the VFP registers to decay to NaNs and zeroes.
+ if ($periodic_reg_random && ($i % 100) == 0) {
+ write_random_register_data($fp_enabled);
+ }
+ progress_update($i);
+ }
+ write_risuop($OP_TESTEND);
+ progress_end();
+ close_bin();
+}
+
+1;
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 2/8] riscv: Generate payload scripts
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 501 insertions(+)
create mode 100644 risugen_riscv.pm
diff --git a/risugen_riscv.pm b/risugen_riscv.pm
new file mode 100644
index 0000000..092c246
--- /dev/null
+++ b/risugen_riscv.pm
@@ -0,0 +1,501 @@
+#!/usr/bin/perl -w
+###############################################################################
+# All rights reserved. This program and the accompanying materials
+# are made available under the terms of the Eclipse Public License v1.0
+# which accompanies this distribution, and is available at
+# http://www.eclipse.org/legal/epl-v10.html
+#
+# Contributors:
+# LIU Zhiwei (PingTouGe) - RISC-V implementation
+# based on Peter Maydell (Linaro) - initial implementation
+###############################################################################
+
+# risugen -- generate a test binary file for use with risu
+# See 'risugen --help' for usage information.
+package risugen_riscv;
+
+use strict;
+use warnings;
+
+use risugen_common;
+
+require Exporter;
+
+our @ISA = qw(Exporter);
+our @EXPORT = qw(write_test_code);
+
+my $periodic_reg_random = 1;
+
+#
+# Maximum alignment restriction permitted for a memory op.
+my $MAXALIGN = 64;
+sub ctz($)
+{
+ my ($imm) = @_;
+ my $cnt = 0;
+
+ if ($imm == 0) {
+ return 0;
+ }
+ while (($imm & 1) == 0) {
+ $cnt++;
+ $imm = $imm >> 1;
+ }
+ return $cnt;
+}
+
+sub decode_li($)
+{
+ my ($imm) = @_;
+ my $cnt = 0;
+ my $idx = 0;
+ my $part = 0;
+ my $next = 0;
+ my %result;
+
+ $next = $imm;
+ # only one lui can not hold
+ while ((($next >> 12) != sextract(($next >> 12) & 0xfffff, 20)) ||
+ (($next & 0xfff) != 0)) {
+ # at the first time, just eat the least 12 bits
+ if ($idx == 0) {
+ $part = sextract($imm & 0xfff, 12);
+ $result{"first"} = $part;
+ } else {
+ $imm = $imm - $part; # clear the part before it
+ $cnt = ctz($imm); # add a shift
+ $imm >>= $cnt;
+ $part = sextract($imm & 0xfff, 12);
+ $result{"mid"}{$idx}{"part"} = $part;
+ $result{"mid"}{$idx}{"cnt"} = $cnt;
+ $next = $imm - $part;
+ }
+ $idx++;
+ }
+ # output a lui
+ $result{"lui"} = sextract(($next >> 12) & 0xfffff, 20);
+ return %result;
+}
+
+# li is implements as Myraid sequences, just the common way here
+sub write_mov_ri($$)
+{
+ my ($rd, $imm) = @_;
+
+ # sequence of li rd, 0x1234567887654321
+ #
+ # 0: 002471b7 lui rd,0x247
+ # 4: 8ad1819b addiw rd,rd,-1875
+ # 8: 00c19193 slli rd,rd,0xc
+ # c: f1118193 addi rd,rd,-239 # 0x246f11
+ # 10: 00d19193 slli rd,rd,0xd
+ # 14: d9518193 addi rd,rd,-619
+ # 18: 00e19193 slli rd,rd,0xe
+ # 1c: 32118193 addi rd,rd,801
+ my %result = decode_li($imm);
+
+ my $len = keys %{$result{"mid"}};
+ my $i = 0;
+
+ # output the last lui
+ insn32(0x00000037 | $rd << 7 | $result{"lui"} << 12);
+ # output the sequence of slli and addi
+ foreach my $key (reverse sort keys %{$result{"mid"}}) {
+ $i++;
+ if ($i == 1) {
+ # output the last addiw
+ insn32(0x0000001b | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"part"} << 20);
+ # slli rd, rd, $result{"mid"}{$key}{"part"}
+ insn32(0x00001013 | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"cnt"} << 20);
+ } else {
+ insn32(0x00000013 | $rd << 7 | $rd << 15 |
+ ($result{"mid"}{$key}{"part"} & 0xfff) << 20);
+ # slli rd, rd, $result{"mid"}{$key}{"part"}
+ insn32(0x00001013 | $rd << 7 | $rd << 15 |
+ $result{"mid"}{$key}{"cnt"} << 20);
+ }
+ }
+ # addi rd, rd, $result{"first"}
+ insn32(0x00000013 | $rd << 7 | $rd << 15 | ($imm & 0xfff) << 20);
+}
+
+sub write_mov_rr($$)
+{
+ my ($rd, $rs1) = @_;
+
+ # addi $rd, $rs1, 0
+ insn32(0x00000013 | $rd << 7 | $rs1 << 15);
+}
+
+sub write_sub_rrr($$$)
+{
+ my ($rd, $rs1, $rs2) = @_;
+
+ # sub $rd, $rs1, $rs2
+ insn32(0x40000033 |$rd << 7 | $rs1 << 15 | $rs2 << 20);
+}
+
+my $OP_COMPARE = 0; # compare registers
+my $OP_TESTEND = 1; # end of test, stop
+my $OP_SETMEMBLOCK = 2; # r0 is address of memory block (8192 bytes)
+my $OP_GETMEMBLOCK = 3; # add the address of memory block to r0
+my $OP_COMPAREMEM = 4; # compare memory block
+
+# write random fp value of passed precision (1=single, 2=double)
+sub write_random_fpreg_var($)
+{
+ my ($precision) = @_;
+ my $randomize_low = 0;
+
+ if ($precision != 1 && $precision != 2) {
+ die "write_random_fpreg: invalid precision.\n";
+ }
+
+ my ($low, $high);
+ my $r = rand(100);
+ if ($r < 5) {
+ # +-0 (5%)
+ $low = $high = 0;
+ $high |= 0x80000000 if (rand() < 0.5);
+ } elsif ($r < 10) {
+ # NaN (5%)
+ # (plus a tiny chance of generating +-Inf)
+ $randomize_low = 1;
+ $high = rand(0xffffffff) | 0x7ff00000;
+ } elsif ($r < 15) {
+ # Infinity (5%)
+ $low = 0;
+ $high = 0x7ff00000;
+ $high |= 0x80000000 if (rand() < 0.5);
+ } elsif ($r < 30) {
+ # Denormalized number (15%)
+ # (plus tiny chance of +-0)
+ $randomize_low = 1;
+ $high = rand(0xffffffff) & ~0x7ff00000;
+ } else {
+ # Normalized number (70%)
+ # (plus a small chance of the other cases)
+ $randomize_low = 1;
+ $high = rand(0xffffffff);
+ }
+
+ for (my $i = 1; $i < $precision; $i++) {
+ if ($randomize_low) {
+ $low = rand(0xffffffff);
+ }
+ insn32($low);
+ }
+ insn32($high);
+}
+
+sub write_random_riscv64_fpdata()
+{
+ # load floating point registers
+ my $align = 16;
+ my $datalen = 32 * 8 + $align;
+ write_pc_adr(10, (4 * 4) + ($align - 1)); # insn 1
+ write_align_reg(10, $align); # insn 2
+ write_jump_fwd($datalen + 4); # insn 3
+
+ # align safety
+ for (my $i = 0; $i < ($align / 4); $i++) {
+ insn32(rand(0xffffffff));
+ }
+
+ # Todo: As the x10 aligned, it won't be the base address of
+ # the interesting numbers.
+ for (my $rt = 0; $rt <= 31; $rt++) {
+ write_random_fpreg_var(2); # double
+ }
+
+ for (my ($rt, $imm) = (0, 0); $rt < 32; $rt++) {
+ # fld rt, x10, imm
+ insn32(0x00003007 | ($imm << 20) | (10 << 15) | ($rt << 7));
+ $imm += 8;
+ }
+}
+
+sub write_random_register_data($)
+{
+ my ($fp_enabled) = @_;
+
+ if ($fp_enabled) {
+ # load floating point
+ write_random_riscv64_fpdata();
+ }
+
+ # general purpose registers
+ for (my $i = 1; $i < 32; $i++) {
+ if ($i != 2 && $i != 3 && $i!= 4) {
+ # TODO full 64 bit pattern instead of 32
+ write_mov_ri($i, rand(0xffffffff));
+ }
+ }
+ write_risuop($OP_COMPARE);
+}
+
+# put PC + offset into a register.
+# this must emit an instruction of 8 bytes.
+sub write_pc_adr($$)
+{
+ my ($rd, $imm) = @_;
+
+ # auipc rd, 0
+ # addi rd, rd, imm
+ insn32(0x00000017 | $rd << 7);
+ insn32(0x00000013 | $imm << 20 | $rd << 15 | $rd << 7);
+}
+
+# clear bits in register to satisfy alignment.
+# Must use exactly 4 instruction-bytes
+sub write_align_reg($$)
+{
+ my ($rd, $align) = @_;
+ my $imm = (-$align) & 0xfff;
+ die "bad alignment!" if ($align < 2);
+
+ # andi rd, rd, ~(align - 1)
+ insn32(0x00007013 | $imm << 20 | $rd << 15 | $rd << 7);
+}
+
+# jump ahead of n bytes starting from next instruction
+sub write_jump_fwd($)
+{
+ my ($len) = @_;
+
+ # 31 30 21 20 19 12 11 7 6 0
+ # imm[20] imm[10:1] imm[11] imm[19:12] rd opcode
+ # 1 10 1 8 5 7
+ # offset[20:1] dest JAL
+ my ($imm20, $imm1, $imm11, $imm12) = (($len & 0x100000) >> 20, ($len & 0x7fe) >> 1,
+ ($len & 0x800) >> 11, ($len & 0xff000) >> 12);
+
+ # jal x0, len
+ insn32(0x0000006f | $imm20 << 31 | $imm1 << 21 | $imm11 << 20 |
+ $imm12 << 12);
+}
+
+sub write_memblock_setup()
+{
+ # Write code which sets up the memory block for loads and stores.
+ # We set r0 to point to a block of 16K length
+ # of random data, aligned to the maximum desired alignment.
+
+ my $align = $MAXALIGN;
+ my $datalen = 16384 + $align;
+ if (($align > 255) || !is_pow_of_2($align) || $align < 4) {
+ die "bad alignment!";
+ }
+
+ # set x10 to (datablock + (align-1)) & ~(align-1)
+ # datablock is at PC + (4 * 5 instructions) = PC + 20
+ write_pc_adr(10, (4 * 5) + ($align - 1)); # insn 1
+ write_align_reg(10, $align); # insn 2
+ write_risuop($OP_SETMEMBLOCK); # insn 3
+ write_jump_fwd($datalen + 4); # insn 4
+
+ for (my $i = 0; $i < $datalen / 4; $i++) {
+ insn32(rand(0xffffffff));
+ }
+ # next:
+}
+
+# Functions used in memory blocks to handle addressing modes.
+# These all have the same basic API: they get called with parameters
+# corresponding to the interesting fields of the instruction,
+# and should generate code to set up the base register to be
+# valid. They must return the register number of the base register.
+# The last (array) parameter lists the registers which are trashed
+# by the instruction (ie which are the targets of the load).
+# This is used to avoid problems when the base reg is a load target.
+
+# Global used to communicate between align(x) and reg() etc.
+my $alignment_restriction;
+
+sub align($)
+{
+ my ($a) = @_;
+ if (!is_pow_of_2($a) || ($a < 0) || ($a > $MAXALIGN)) {
+ die "bad align() value $a\n";
+ }
+ $alignment_restriction = $a;
+}
+
+sub write_get_offset()
+{
+ # Emit code to get a random offset within the memory block, of the
+ # right alignment, into r0
+ # We require the offset to not be within 256 bytes of either
+ # end, to (more than) allow for the worst case data transfer, which is
+ # 16 * 64 bit regs
+ my $offset = (rand(16384 - 8192) + 4096) & ~($alignment_restriction - 1);
+ write_mov_ri(10, $offset);
+ write_risuop($OP_GETMEMBLOCK);
+}
+
+sub reg($@)
+{
+ my ($base, @trashed) = @_;
+ write_get_offset();
+ # Now x10 is the address we want to do the access to,
+ # so just move it into the basereg
+ if ($base != 10) {
+ write_mov_rr($base, 10);
+ write_mov_ri(10, 0);
+ }
+ if (grep $_ == $base, @trashed) {
+ return -1;
+ }
+ return $base;
+}
+
+sub reg_plus_imm($$@)
+{
+ # Handle reg + immediate addressing mode
+ my ($base, $imm, @trashed) = @_;
+ if ($imm == 0) {
+ return reg($base, @trashed);
+ }
+
+ write_get_offset();
+ # Now x10 is the address we want to do the access to,
+ # so set the basereg by doing the inverse of the
+ # addressing mode calculation, ie base = x10 - imm
+ # We could do this more cleverly with a sub immediate.
+ if ($base != 10) {
+ write_mov_ri($base, $imm);
+ write_sub_rrr($base, 10, $base);
+ # Clear x10 to avoid register compare mismatches
+ # when the memory block location differs between machines.
+ write_mov_ri(10, 0);
+ } else {
+ # We borrow x11 as a temporary (not a problem
+ # as long as we don't leave anything in a register
+ # which depends on the location of the memory block)
+ write_mov_ri(11, $imm);
+ write_sub_rrr($base, 10, 11);
+ }
+ if (grep $_ == $base, @trashed) {
+ return -1;
+ }
+ return $base;
+}
+
+sub gen_one_insn($)
+{
+ # Given an instruction-details array, generate an instruction
+ my $constraintfailures = 0;
+
+ INSN: while(1) {
+ my ($rec) = @_;
+ my $insn = int(rand(0xffffffff));
+ my $insnname = $rec->{name};
+ my $insnwidth = $rec->{width};
+ my $fixedbits = $rec->{fixedbits};
+ my $fixedbitmask = $rec->{fixedbitmask};
+ my $constraint = $rec->{blocks}{"constraints"};
+ my $memblock = $rec->{blocks}{"memory"};
+
+ $insn &= ~$fixedbitmask;
+ $insn |= $fixedbits;
+
+ if (defined $constraint) {
+ # user-specified constraint: evaluate in an environment
+ # with variables set corresponding to the variable fields.
+ my $v = eval_with_fields($insnname, $insn, $rec, "constraints", $constraint);
+ if (!$v) {
+ $constraintfailures++;
+ if ($constraintfailures > 10000) {
+ print "10000 consecutive constraint failures for $insnname constraints string:\n$constraint\n";
+ exit (1);
+ }
+ next INSN;
+ }
+ }
+
+ # OK, we got a good one
+ $constraintfailures = 0;
+
+ my $basereg;
+
+ if (defined $memblock) {
+ # This is a load or store. We simply evaluate the block,
+ # which is expected to be a call to a function which emits
+ # the code to set up the base register and returns the
+ # number of the base register.
+ # we use 16 for riscv64, although often unnecessary and overkill.
+ align(16);
+ $basereg = eval_with_fields($insnname, $insn, $rec, "memory", $memblock);
+ }
+
+ insn32($insn);
+
+ if (defined $memblock) {
+ # Clean up following a memory access instruction:
+ # we need to turn the (possibly written-back) basereg
+ # into an offset from the base of the memory block,
+ # to avoid making register values depend on memory layout.
+ # $basereg -1 means the basereg was a target of a load
+ # (and so it doesn't contain a memory address after the op)
+ if ($basereg != -1) {
+ write_mov_ri($basereg, 0);
+ }
+ }
+ return;
+ }
+}
+
+sub write_risuop($)
+{
+ # instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED
+ my ($op) = @_;
+ insn32(0x0000006b | $op << 8);
+}
+
+sub write_test_code($)
+{
+ my ($params) = @_;
+
+ my $numinsns = $params->{ 'numinsns' };
+ my $fp_enabled = $params->{ 'fp_enabled' };
+ my $outfile = $params->{ 'outfile' };
+
+ my %insn_details = %{ $params->{ 'details' } };
+ my @keys = @{ $params->{ 'keys' } };
+
+ print "Enter write code", "\n";
+ open_bin($outfile);
+
+ # TODO better random number generator?
+ srand(0);
+
+ print "Generating code using patterns: @keys...\n";
+ progress_start(78, $numinsns);
+
+ if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) {
+ write_memblock_setup();
+ }
+
+ # memblock setup doesn't clean its registers, so this must come afterwards.
+ write_random_register_data($fp_enabled);
+
+ for my $i (1..$numinsns) {
+ my $insn_enc = $keys[int rand (@keys)];
+ #dump_insn_details($insn_enc, $insn_details{$insn_enc});
+ gen_one_insn($insn_details{$insn_enc});
+ write_risuop($OP_COMPARE);
+ # Rewrite the registers periodically. This avoids the tendency
+ # for the VFP registers to decay to NaNs and zeroes.
+ if ($periodic_reg_random && ($i % 100) == 0) {
+ write_random_register_data($fp_enabled);
+ }
+ progress_update($i);
+ }
+ write_risuop($OP_TESTEND);
+ progress_end();
+ close_bin();
+}
+
+1;
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 3/8] riscv: Define riscv struct reginfo
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 risu_reginfo_riscv64.h
diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h
new file mode 100644
index 0000000..7d365a8
--- /dev/null
+++ b/risu_reginfo_riscv64.h
@@ -0,0 +1,29 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(PingTouGe) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#ifndef RISU_REGINFO_RISCV64_H
+#define RISU_REGINFO_RISCV64_H
+
+struct reginfo {
+ uint64_t fault_address;
+ uint64_t regs[32];
+ uint64_t fregs[32];
+ uint64_t sp;
+ uint64_t pc;
+ uint32_t flags;
+ uint32_t faulting_insn;
+
+ /* FP */
+ uint32_t fcsr;
+};
+
+#endif /* RISU_REGINFO_RISCV64_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 3/8] riscv: Define riscv struct reginfo
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 risu_reginfo_riscv64.h
diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h
new file mode 100644
index 0000000..7d365a8
--- /dev/null
+++ b/risu_reginfo_riscv64.h
@@ -0,0 +1,29 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(PingTouGe) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#ifndef RISU_REGINFO_RISCV64_H
+#define RISU_REGINFO_RISCV64_H
+
+struct reginfo {
+ uint64_t fault_address;
+ uint64_t regs[32];
+ uint64_t fregs[32];
+ uint64_t sp;
+ uint64_t pc;
+ uint32_t flags;
+ uint32_t faulting_insn;
+
+ /* FP */
+ uint32_t fcsr;
+};
+
+#endif /* RISU_REGINFO_RISCV64_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 4/8] riscv: Implement payload load interfaces
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.c | 134 +++++++++++++++++++++++++++++++++++++++++
risu_riscv64.c | 47 +++++++++++++++
2 files changed, 181 insertions(+)
create mode 100644 risu_reginfo_riscv64.c
create mode 100644 risu_riscv64.c
diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c
new file mode 100644
index 0000000..cfa9889
--- /dev/null
+++ b/risu_reginfo_riscv64.c
@@ -0,0 +1,134 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei (PingTouGe) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#include <stdio.h>
+#include <ucontext.h>
+#include <string.h>
+#include <signal.h> /* for FPSIMD_MAGIC */
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <inttypes.h>
+#include <assert.h>
+#include <sys/prctl.h>
+
+#include "risu.h"
+#include "risu_reginfo_riscv64.h"
+
+const struct option * const arch_long_opts;
+const char * const arch_extra_help;
+
+void process_arch_opt(int opt, const char *arg)
+{
+ abort();
+}
+
+const int reginfo_size(void)
+{
+ return sizeof(struct reginfo);
+}
+
+/* reginfo_init: initialize with a ucontext */
+void reginfo_init(struct reginfo *ri, ucontext_t *uc)
+{
+ int i;
+ union __riscv_mc_fp_state *fp;
+ /* necessary to be able to compare with memcmp later */
+ memset(ri, 0, sizeof(*ri));
+
+ for (i = 0; i < 32; i++) {
+ ri->regs[i] = uc->uc_mcontext.__gregs[i];
+ }
+
+ ri->sp = 0xdeadbeefdeadbeef;
+ ri->regs[2] = 0xdeadbeefdeadbeef;
+ ri->regs[3] = 0xdeadbeefdeadbeef;
+ ri->regs[4] = 0xdeadbeefdeadbeef;
+ ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address;
+ ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]);
+ fp = &uc->uc_mcontext.__fpregs;
+ ri->fcsr = fp->__d.__fcsr;
+
+ for (i = 0; i < 32; i++) {
+ ri->fregs[i] = fp->__d.__f[i];
+ }
+}
+
+/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
+int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
+{
+ return memcmp(r1, r2, reginfo_size()) == 0;
+}
+
+/* reginfo_dump: print state to a stream, returns nonzero on success */
+int reginfo_dump(struct reginfo *ri, FILE * f)
+{
+ int i;
+ fprintf(f, " faulting insn %08x\n", ri->faulting_insn);
+
+ for (i = 1; i < 32; i++) {
+ fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]);
+ }
+
+ fprintf(f, " sp : %016" PRIx64 "\n", ri->sp);
+ fprintf(f, " pc : %016" PRIx64 "\n", ri->pc);
+ fprintf(f, " fcsr : %08x\n", ri->fcsr);
+
+ for (i = 0; i < 32; i++) {
+ fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]);
+ }
+
+ return !ferror(f);
+}
+
+/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
+int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
+{
+ int i;
+ fprintf(f, "mismatch detail (master : apprentice):\n");
+ if (m->faulting_insn != a->faulting_insn) {
+ fprintf(f, " faulting insn mismatch %08x vs %08x\n",
+ m->faulting_insn, a->faulting_insn);
+ }
+ for (i = 1; i < 32; i++) {
+ if (m->regs[i] != a->regs[i]) {
+ fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
+ i, m->regs[i], a->regs[i]);
+ }
+ }
+
+ if (m->sp != a->sp) {
+ fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n",
+ m->sp, a->sp);
+ }
+
+ if (m->pc != a->pc) {
+ fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n",
+ m->pc, a->pc);
+ }
+
+ if (m->fcsr != a->fcsr) {
+ fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr);
+ }
+
+ for (i = 0; i < 32; i++) {
+ if (m->fregs[i] != a->fregs[i]) {
+ fprintf(f, " F%-2d : "
+ "%016" PRIx64 " vs "
+ "%016" PRIx64 "\n", i,
+ (uint64_t) m->fregs[i],
+ (uint64_t) a->fregs[i]);
+ }
+ }
+
+ return !ferror(f);
+}
diff --git a/risu_riscv64.c b/risu_riscv64.c
new file mode 100644
index 0000000..f742a40
--- /dev/null
+++ b/risu_riscv64.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(Linaro) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#include "risu.h"
+
+void advance_pc(void *vuc)
+{
+ ucontext_t *uc = vuc;
+ uc->uc_mcontext.__gregs[0] += 4;
+}
+
+void set_ucontext_paramreg(void *vuc, uint64_t value)
+{
+ ucontext_t *uc = vuc;
+ uc->uc_mcontext.__gregs[10] = value;
+}
+
+uint64_t get_reginfo_paramreg(struct reginfo *ri)
+{
+ return ri->regs[10];
+}
+
+int get_risuop(struct reginfo *ri)
+{
+ /* Return the risuop we have been asked to do
+ * (or -1 if this was a SIGILL for a non-risuop insn)
+ */
+ uint32_t insn = ri->faulting_insn;
+ uint32_t op = (insn & 0xf00) >> 8;
+ uint32_t key = insn & ~0xf00;
+ uint32_t risukey = 0x0000006b;
+ return (key != risukey) ? -1 : op;
+}
+
+uintptr_t get_pc(struct reginfo *ri)
+{
+ return ri->pc;
+}
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 4/8] riscv: Implement payload load interfaces
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.c | 134 +++++++++++++++++++++++++++++++++++++++++
risu_riscv64.c | 47 +++++++++++++++
2 files changed, 181 insertions(+)
create mode 100644 risu_reginfo_riscv64.c
create mode 100644 risu_riscv64.c
diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c
new file mode 100644
index 0000000..cfa9889
--- /dev/null
+++ b/risu_reginfo_riscv64.c
@@ -0,0 +1,134 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei (PingTouGe) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#include <stdio.h>
+#include <ucontext.h>
+#include <string.h>
+#include <signal.h> /* for FPSIMD_MAGIC */
+#include <stdlib.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include <inttypes.h>
+#include <assert.h>
+#include <sys/prctl.h>
+
+#include "risu.h"
+#include "risu_reginfo_riscv64.h"
+
+const struct option * const arch_long_opts;
+const char * const arch_extra_help;
+
+void process_arch_opt(int opt, const char *arg)
+{
+ abort();
+}
+
+const int reginfo_size(void)
+{
+ return sizeof(struct reginfo);
+}
+
+/* reginfo_init: initialize with a ucontext */
+void reginfo_init(struct reginfo *ri, ucontext_t *uc)
+{
+ int i;
+ union __riscv_mc_fp_state *fp;
+ /* necessary to be able to compare with memcmp later */
+ memset(ri, 0, sizeof(*ri));
+
+ for (i = 0; i < 32; i++) {
+ ri->regs[i] = uc->uc_mcontext.__gregs[i];
+ }
+
+ ri->sp = 0xdeadbeefdeadbeef;
+ ri->regs[2] = 0xdeadbeefdeadbeef;
+ ri->regs[3] = 0xdeadbeefdeadbeef;
+ ri->regs[4] = 0xdeadbeefdeadbeef;
+ ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address;
+ ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]);
+ fp = &uc->uc_mcontext.__fpregs;
+ ri->fcsr = fp->__d.__fcsr;
+
+ for (i = 0; i < 32; i++) {
+ ri->fregs[i] = fp->__d.__f[i];
+ }
+}
+
+/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */
+int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2)
+{
+ return memcmp(r1, r2, reginfo_size()) == 0;
+}
+
+/* reginfo_dump: print state to a stream, returns nonzero on success */
+int reginfo_dump(struct reginfo *ri, FILE * f)
+{
+ int i;
+ fprintf(f, " faulting insn %08x\n", ri->faulting_insn);
+
+ for (i = 1; i < 32; i++) {
+ fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]);
+ }
+
+ fprintf(f, " sp : %016" PRIx64 "\n", ri->sp);
+ fprintf(f, " pc : %016" PRIx64 "\n", ri->pc);
+ fprintf(f, " fcsr : %08x\n", ri->fcsr);
+
+ for (i = 0; i < 32; i++) {
+ fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]);
+ }
+
+ return !ferror(f);
+}
+
+/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */
+int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f)
+{
+ int i;
+ fprintf(f, "mismatch detail (master : apprentice):\n");
+ if (m->faulting_insn != a->faulting_insn) {
+ fprintf(f, " faulting insn mismatch %08x vs %08x\n",
+ m->faulting_insn, a->faulting_insn);
+ }
+ for (i = 1; i < 32; i++) {
+ if (m->regs[i] != a->regs[i]) {
+ fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
+ i, m->regs[i], a->regs[i]);
+ }
+ }
+
+ if (m->sp != a->sp) {
+ fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n",
+ m->sp, a->sp);
+ }
+
+ if (m->pc != a->pc) {
+ fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n",
+ m->pc, a->pc);
+ }
+
+ if (m->fcsr != a->fcsr) {
+ fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr);
+ }
+
+ for (i = 0; i < 32; i++) {
+ if (m->fregs[i] != a->fregs[i]) {
+ fprintf(f, " F%-2d : "
+ "%016" PRIx64 " vs "
+ "%016" PRIx64 "\n", i,
+ (uint64_t) m->fregs[i],
+ (uint64_t) a->fregs[i]);
+ }
+ }
+
+ return !ferror(f);
+}
diff --git a/risu_riscv64.c b/risu_riscv64.c
new file mode 100644
index 0000000..f742a40
--- /dev/null
+++ b/risu_riscv64.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(Linaro) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#include "risu.h"
+
+void advance_pc(void *vuc)
+{
+ ucontext_t *uc = vuc;
+ uc->uc_mcontext.__gregs[0] += 4;
+}
+
+void set_ucontext_paramreg(void *vuc, uint64_t value)
+{
+ ucontext_t *uc = vuc;
+ uc->uc_mcontext.__gregs[10] = value;
+}
+
+uint64_t get_reginfo_paramreg(struct reginfo *ri)
+{
+ return ri->regs[10];
+}
+
+int get_risuop(struct reginfo *ri)
+{
+ /* Return the risuop we have been asked to do
+ * (or -1 if this was a SIGILL for a non-risuop insn)
+ */
+ uint32_t insn = ri->faulting_insn;
+ uint32_t op = (insn & 0xf00) >> 8;
+ uint32_t key = insn & ~0xf00;
+ uint32_t risukey = 0x0000006b;
+ return (key != risukey) ? -1 : op;
+}
+
+uintptr_t get_pc(struct reginfo *ri)
+{
+ return ri->pc;
+}
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 5/8] riscv: Add standard test case
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 test_riscv64.s
diff --git a/test_riscv64.s b/test_riscv64.s
new file mode 100644
index 0000000..5a8279f
--- /dev/null
+++ b/test_riscv64.s
@@ -0,0 +1,85 @@
+/*****************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei (PingTouGe) - initial implementation
+ * based on test_arm.s by Peter Maydell
+ *****************************************************************************/
+
+/* Initialise the gp regs */
+li x1, 1
+#li x2, 2 # stack pointer
+#li x3, 3 # global pointer
+#li x4, 4 # thread pointer
+li x5, 5
+li x6, 6
+li x7, 7
+li x8, 8
+li x9, 9
+li x10, 10
+li x11, 11
+li x12, 12
+li x13, 13
+li x14, 14
+li x15, 15
+li x16, 16
+li x17, 17
+li x18, 18
+li x19, 19
+li x20, 20
+li x21, 21
+li x22, 22
+li x23, 23
+li x24, 24
+li x25, 25
+li x26, 26
+li x27, 27
+li x28, 28
+li x29, 29
+li x30, 30
+li x31, 30
+
+/* Initialise the fp regs */
+fcvt.d.lu f0, x0
+fcvt.d.lu f1, x1
+#fcvt.d.lu f2, x2
+fcvt.d.lu f3, x3
+fcvt.d.lu f4, x4
+fcvt.d.lu f5, x5
+fcvt.d.lu f6, x6
+fcvt.d.lu f7, x7
+fcvt.d.lu f8, x8
+fcvt.d.lu f9, x9
+fcvt.d.lu f10, x10
+fcvt.d.lu f11, x11
+fcvt.d.lu f12, x12
+fcvt.d.lu f13, x13
+fcvt.d.lu f14, x14
+fcvt.d.lu f15, x15
+fcvt.d.lu f16, x16
+fcvt.d.lu f17, x17
+fcvt.d.lu f18, x18
+fcvt.d.lu f19, x19
+fcvt.d.lu f20, x20
+fcvt.d.lu f21, x21
+fcvt.d.lu f22, x22
+fcvt.d.lu f23, x23
+fcvt.d.lu f24, x24
+fcvt.d.lu f25, x25
+fcvt.d.lu f26, x26
+fcvt.d.lu f27, x27
+fcvt.d.lu f28, x28
+fcvt.d.lu f29, x29
+fcvt.d.lu f30, x30
+fcvt.d.lu f31, x31
+
+/* do compare.
+ * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED
+ */
+.int 0x0000006b
+/* exit test */
+.int 0x0000016b
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 5/8] riscv: Add standard test case
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 test_riscv64.s
diff --git a/test_riscv64.s b/test_riscv64.s
new file mode 100644
index 0000000..5a8279f
--- /dev/null
+++ b/test_riscv64.s
@@ -0,0 +1,85 @@
+/*****************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei (PingTouGe) - initial implementation
+ * based on test_arm.s by Peter Maydell
+ *****************************************************************************/
+
+/* Initialise the gp regs */
+li x1, 1
+#li x2, 2 # stack pointer
+#li x3, 3 # global pointer
+#li x4, 4 # thread pointer
+li x5, 5
+li x6, 6
+li x7, 7
+li x8, 8
+li x9, 9
+li x10, 10
+li x11, 11
+li x12, 12
+li x13, 13
+li x14, 14
+li x15, 15
+li x16, 16
+li x17, 17
+li x18, 18
+li x19, 19
+li x20, 20
+li x21, 21
+li x22, 22
+li x23, 23
+li x24, 24
+li x25, 25
+li x26, 26
+li x27, 27
+li x28, 28
+li x29, 29
+li x30, 30
+li x31, 30
+
+/* Initialise the fp regs */
+fcvt.d.lu f0, x0
+fcvt.d.lu f1, x1
+#fcvt.d.lu f2, x2
+fcvt.d.lu f3, x3
+fcvt.d.lu f4, x4
+fcvt.d.lu f5, x5
+fcvt.d.lu f6, x6
+fcvt.d.lu f7, x7
+fcvt.d.lu f8, x8
+fcvt.d.lu f9, x9
+fcvt.d.lu f10, x10
+fcvt.d.lu f11, x11
+fcvt.d.lu f12, x12
+fcvt.d.lu f13, x13
+fcvt.d.lu f14, x14
+fcvt.d.lu f15, x15
+fcvt.d.lu f16, x16
+fcvt.d.lu f17, x17
+fcvt.d.lu f18, x18
+fcvt.d.lu f19, x19
+fcvt.d.lu f20, x20
+fcvt.d.lu f21, x21
+fcvt.d.lu f22, x22
+fcvt.d.lu f23, x23
+fcvt.d.lu f24, x24
+fcvt.d.lu f25, x25
+fcvt.d.lu f26, x26
+fcvt.d.lu f27, x27
+fcvt.d.lu f28, x28
+fcvt.d.lu f29, x29
+fcvt.d.lu f30, x30
+fcvt.d.lu f31, x31
+
+/* do compare.
+ * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED
+ */
+.int 0x0000006b
+/* exit test */
+.int 0x0000016b
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 6/8] riscv: Add configure script
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
For RV64 risu, make CFLAGS="-march=rv64g"
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
configure | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index ca2d7db..5c9e967 100755
--- a/configure
+++ b/configure
@@ -58,6 +58,8 @@ guess_arch() {
ARCH="m68k"
elif check_define __powerpc64__ ; then
ARCH="ppc64"
+ elif check_define __riscv ; then
+ ARCH="riscv64"
else
echo "This cpu is not supported by risu. Try -h. " >&2
exit 1
@@ -139,7 +141,7 @@ Some influential environment variables:
prefixed with the given string.
ARCH force target architecture instead of trying to detect it.
- Valid values=[arm|aarch64|ppc64|ppc64le|m68k]
+ Valid values=[arm|aarch64|ppc64|ppc64le|m68k|riscv64]
CC C compiler command
CFLAGS C compiler flags
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 6/8] riscv: Add configure script
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
For RV64 risu, make CFLAGS="-march=rv64g"
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
configure | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index ca2d7db..5c9e967 100755
--- a/configure
+++ b/configure
@@ -58,6 +58,8 @@ guess_arch() {
ARCH="m68k"
elif check_define __powerpc64__ ; then
ARCH="ppc64"
+ elif check_define __riscv ; then
+ ARCH="riscv64"
else
echo "This cpu is not supported by risu. Try -h. " >&2
exit 1
@@ -139,7 +141,7 @@ Some influential environment variables:
prefixed with the given string.
ARCH force target architecture instead of trying to detect it.
- Valid values=[arm|aarch64|ppc64|ppc64le|m68k]
+ Valid values=[arm|aarch64|ppc64|ppc64le|m68k|riscv64]
CC C compiler command
CFLAGS C compiler flags
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 7/8] riscv: Add RV64M instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/riscv64.risu b/riscv64.risu
index 98141ab..f006dc8 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+@RV64M
+
+MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 7/8] riscv: Add RV64M instructions description
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/riscv64.risu b/riscv64.risu
index 98141ab..f006dc8 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+@RV64M
+
+MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 8/8] riscv: Add RV64F instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-04-30 7:21 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: qemu-riscv, richard.henderson, qemu-devel, wxy194768,
wenmeng_zhang, palmer, alistair23, alex.bennee, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/riscv64.risu b/riscv64.risu
index f006dc8..0b81dfb 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -181,4 +181,82 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+@RV64F
+FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011
+
+FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111
+
+FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011
+
+FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111
+
+FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011
+
+FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011
+
+FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011
+
+FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011
+
+FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011
+
+FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011
+
+FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FMV_X_W RISCV 1110000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
+
+FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [RFC PATCH 8/8] riscv: Add RV64F instructions description
@ 2020-04-30 7:21 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-04-30 7:21 UTC (permalink / raw)
To: peter.maydell
Cc: richard.henderson, alistair23, palmer, wenmeng_zhang, wxy194768,
qemu-devel, alex.bennee, qemu-riscv, LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/riscv64.risu b/riscv64.risu
index f006dc8..0b81dfb 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -181,4 +181,82 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+@RV64F
+FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0000111 \
+!constraints { $rs1 != 0 && $rs1 != 2 && $rs1 !=3 && $rs1 != 4 && $rs2 != 2} \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011
+
+FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111
+
+FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011
+
+FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111
+
+FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011
+
+FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011
+
+FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011
+
+FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011
+
+FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011
+
+FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011
+
+FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011
+
+FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FMV_X_W RISCV 1110000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
+
+FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { $rs1 != 2 }
+
+FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
+
+FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
+
+FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
--
2.23.0
^ permalink raw reply related [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 0/8] RISCV risu porting
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 16:30 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 16:30 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> It's some difficult when I try to support RV32, because it's very
> similiar to RV64, so I can't make two .risu files like arm.risu and
> aarch64.risu.
You could a command-line parameter, like --be or --sve for this.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 0/8] RISCV risu porting
@ 2020-05-11 16:30 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 16:30 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> It's some difficult when I try to support RV32, because it's very
> similiar to RV64, so I can't make two .risu files like arm.risu and
> aarch64.risu.
You could a command-line parameter, like --be or --sve for this.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 16:39 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 16:39 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +LUI RISCV imm:20 rd:5 0110111 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this. e.g. greg($rd) and
gbase($rs1) (including $0). It would keep the constraints smaller, and avoid
mistakes.
These functions would go into risugen_riscv.pm.
> +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
sp, and not gp and tp as well?
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
@ 2020-05-11 16:39 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 16:39 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +LUI RISCV imm:20 rd:5 0110111 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
I think it would be helpful to add a function for this. e.g. greg($rd) and
gbase($rs1) (including $0). It would keep the constraints smaller, and avoid
mistakes.
These functions would go into risugen_riscv.pm.
> +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
sp, and not gp and tp as well?
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 17:40 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 17:40 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> + # sequence of li rd, 0x1234567887654321
> + #
> + # 0: 002471b7 lui rd,0x247
> + # 4: 8ad1819b addiw rd,rd,-1875
> + # 8: 00c19193 slli rd,rd,0xc
> + # c: f1118193 addi rd,rd,-239 # 0x246f11
> + # 10: 00d19193 slli rd,rd,0xd
> + # 14: d9518193 addi rd,rd,-619
> + # 18: 00e19193 slli rd,rd,0xe
> + # 1c: 32118193 addi rd,rd,801
You don't really need to use addiw. Removing that special case would really
simplify this.
> +sub write_memblock_setup()
> +{
> + # Write code which sets up the memory block for loads and stores.
> + # We set r0 to point to a block of 16K length
> + # of random data, aligned to the maximum desired alignment.
> +
> + my $align = $MAXALIGN;
> + my $datalen = 16384 + $align;
risu.h:#define MEMBLOCKLEN 8192
Why are you using 16384?
Also, typo -- you're setting r10 not r0, obviously.
The rest looks fine.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
@ 2020-05-11 17:40 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 17:40 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> + # sequence of li rd, 0x1234567887654321
> + #
> + # 0: 002471b7 lui rd,0x247
> + # 4: 8ad1819b addiw rd,rd,-1875
> + # 8: 00c19193 slli rd,rd,0xc
> + # c: f1118193 addi rd,rd,-239 # 0x246f11
> + # 10: 00d19193 slli rd,rd,0xd
> + # 14: d9518193 addi rd,rd,-619
> + # 18: 00e19193 slli rd,rd,0xe
> + # 1c: 32118193 addi rd,rd,801
You don't really need to use addiw. Removing that special case would really
simplify this.
> +sub write_memblock_setup()
> +{
> + # Write code which sets up the memory block for loads and stores.
> + # We set r0 to point to a block of 16K length
> + # of random data, aligned to the maximum desired alignment.
> +
> + my $align = $MAXALIGN;
> + my $datalen = 16384 + $align;
risu.h:#define MEMBLOCKLEN 8192
Why are you using 16384?
Also, typo -- you're setting r10 not r0, obviously.
The rest looks fine.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 3/8] riscv: Define riscv struct reginfo
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 17:42 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 17:42 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +struct reginfo {
> + uint64_t fault_address;
> + uint64_t regs[32];
> + uint64_t fregs[32];
> + uint64_t sp;
> + uint64_t pc;
> + uint32_t flags;
> + uint32_t faulting_insn;
> +
> + /* FP */
> + uint32_t fcsr;
> +};
There's no need for a separate sp field, since that's regs[2].
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 3/8] riscv: Define riscv struct reginfo
@ 2020-05-11 17:42 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 17:42 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +struct reginfo {
> + uint64_t fault_address;
> + uint64_t regs[32];
> + uint64_t fregs[32];
> + uint64_t sp;
> + uint64_t pc;
> + uint32_t flags;
> + uint32_t faulting_insn;
> +
> + /* FP */
> + uint32_t fcsr;
> +};
There's no need for a separate sp field, since that's regs[2].
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 18:03 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:03 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +void reginfo_init(struct reginfo *ri, ucontext_t *uc)
> +{
> + int i;
> + union __riscv_mc_fp_state *fp;
> + /* necessary to be able to compare with memcmp later */
> + memset(ri, 0, sizeof(*ri));
> +
> + for (i = 0; i < 32; i++) {
> + ri->regs[i] = uc->uc_mcontext.__gregs[i];
> + }
> +
> + ri->sp = 0xdeadbeefdeadbeef;
> + ri->regs[2] = 0xdeadbeefdeadbeef;
> + ri->regs[3] = 0xdeadbeefdeadbeef;
> + ri->regs[4] = 0xdeadbeefdeadbeef;
> + ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address;
> + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]);
> + fp = &uc->uc_mcontext.__fpregs;
> + ri->fcsr = fp->__d.__fcsr;
> +
> + for (i = 0; i < 32; i++) {
> + ri->fregs[i] = fp->__d.__f[i];
> + }
> +}
Perhaps wrap the fp bits here in
#if __riscv_flen == 64
ri->fcsr = fp->__d.__fscr;
...
#else
# error "Unsupported fp length"
#endif
> + if (m->regs[i] != a->regs[i]) {
> + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
> + i, m->regs[i], a->regs[i]);
> + }
riscv doesn't name its registers with an x.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
@ 2020-05-11 18:03 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:03 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +void reginfo_init(struct reginfo *ri, ucontext_t *uc)
> +{
> + int i;
> + union __riscv_mc_fp_state *fp;
> + /* necessary to be able to compare with memcmp later */
> + memset(ri, 0, sizeof(*ri));
> +
> + for (i = 0; i < 32; i++) {
> + ri->regs[i] = uc->uc_mcontext.__gregs[i];
> + }
> +
> + ri->sp = 0xdeadbeefdeadbeef;
> + ri->regs[2] = 0xdeadbeefdeadbeef;
> + ri->regs[3] = 0xdeadbeefdeadbeef;
> + ri->regs[4] = 0xdeadbeefdeadbeef;
> + ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address;
> + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]);
> + fp = &uc->uc_mcontext.__fpregs;
> + ri->fcsr = fp->__d.__fcsr;
> +
> + for (i = 0; i < 32; i++) {
> + ri->fregs[i] = fp->__d.__f[i];
> + }
> +}
Perhaps wrap the fp bits here in
#if __riscv_flen == 64
ri->fcsr = fp->__d.__fscr;
...
#else
# error "Unsupported fp length"
#endif
> + if (m->regs[i] != a->regs[i]) {
> + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
> + i, m->regs[i], a->regs[i]);
> + }
riscv doesn't name its registers with an x.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 5/8] riscv: Add standard test case
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 18:04 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:04 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 test_riscv64.s
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 5/8] riscv: Add standard test case
@ 2020-05-11 18:04 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:04 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 test_riscv64.s
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 18:06 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:06 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +++ b/configure
> @@ -58,6 +58,8 @@ guess_arch() {
> ARCH="m68k"
> elif check_define __powerpc64__ ; then
> ARCH="ppc64"
> + elif check_define __riscv ; then
> + ARCH="riscv64"
> else
> echo "This cpu is not supported by risu. Try -h. " >&2
> exit 1
Why "riscv64" and not "riscv"?
You can't really say more without checking __riscv_xlen.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
@ 2020-05-11 18:06 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:06 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +++ b/configure
> @@ -58,6 +58,8 @@ guess_arch() {
> ARCH="m68k"
> elif check_define __powerpc64__ ; then
> ARCH="ppc64"
> + elif check_define __riscv ; then
> + ARCH="riscv64"
> else
> echo "This cpu is not supported by risu. Try -h. " >&2
> exit 1
Why "riscv64" and not "riscv"?
You can't really say more without checking __riscv_xlen.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
2020-05-11 18:03 ` Richard Henderson
@ 2020-05-11 18:07 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:07 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 5/11/20 11:03 AM, Richard Henderson wrote:
>> + if (m->regs[i] != a->regs[i]) {
>> + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
>> + i, m->regs[i], a->regs[i]);
>> + }
>
> riscv doesn't name its registers with an x.
Duh. It does. Nevermind this.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 4/8] riscv: Implement payload load interfaces
@ 2020-05-11 18:07 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:07 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 5/11/20 11:03 AM, Richard Henderson wrote:
>> + if (m->regs[i] != a->regs[i]) {
>> + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
>> + i, m->regs[i], a->regs[i]);
>> + }
>
> riscv doesn't name its registers with an x.
Duh. It does. Nevermind this.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 18:11 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:11 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
Interesting question here: Do we really want to avoid the reserved rounding
modes, or do we want to verify that we raise an invalid operand exception?
I guess I'm fine with it either way.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
@ 2020-05-11 18:11 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:11 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> +
> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
Interesting question here: Do we really want to avoid the reserved rounding
modes, or do we want to verify that we raise an invalid operand exception?
I guess I'm fine with it either way.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 7/8] riscv: Add RV64M instructions description
2020-04-30 7:21 ` LIU Zhiwei
@ 2020-05-11 18:12 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:12 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/riscv64.risu b/riscv64.risu
> index 98141ab..f006dc8 100644
> --- a/riscv64.risu
> +++ b/riscv64.risu
> @@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
>
> SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
> !constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
> +
> +@RV64M
> +
> +MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
> +
Modulo the use of a helper function,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 7/8] riscv: Add RV64M instructions description
@ 2020-05-11 18:12 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-11 18:12 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 4/30/20 12:21 AM, LIU Zhiwei wrote:
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/riscv64.risu b/riscv64.risu
> index 98141ab..f006dc8 100644
> --- a/riscv64.risu
> +++ b/riscv64.risu
> @@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
>
> SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
> !constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
> +
> +@RV64M
> +
> +MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
> +
Modulo the use of a helper function,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 0/8] RISCV risu porting
2020-05-11 16:30 ` Richard Henderson
@ 2020-05-19 9:44 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-19 9:44 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
[-- Attachment #1: Type: text/plain, Size: 765 bytes --]
On 2020/5/12 0:30, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> It's some difficult when I try to support RV32, because it's very
>> similiar to RV64, so I can't make two .risu files like arm.risu and
>> aarch64.risu.
> You could a command-line parameter, like --be or --sve for this.
Yes. I should add a "--xlen" parameter to specify the general register
length in risugen_riscv.pm.
Besides, I should modify current riscv64.risu.
For instructions in RV32 and RV64:
LB RV32_64 imm:12 rs1:5 000 rd:5 0000011
For RV64 only instructions:
LD RV64 imm:12 rs1:5 011 rd:5 0000011
So I can generate RV32 instructions through --pattern '*.RV32.*', and
the RV64 instructions through --pattern '.*RV64.*'.
Best Regards,
Zhiwei
>
> r~
[-- Attachment #2: Type: text/html, Size: 1538 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 0/8] RISCV risu porting
@ 2020-05-19 9:44 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-19 9:44 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
[-- Attachment #1: Type: text/plain, Size: 765 bytes --]
On 2020/5/12 0:30, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> It's some difficult when I try to support RV32, because it's very
>> similiar to RV64, so I can't make two .risu files like arm.risu and
>> aarch64.risu.
> You could a command-line parameter, like --be or --sve for this.
Yes. I should add a "--xlen" parameter to specify the general register
length in risugen_riscv.pm.
Besides, I should modify current riscv64.risu.
For instructions in RV32 and RV64:
LB RV32_64 imm:12 rs1:5 000 rd:5 0000011
For RV64 only instructions:
LD RV64 imm:12 rs1:5 011 rd:5 0000011
So I can generate RV32 instructions through --pattern '*.RV32.*', and
the RV64 instructions through --pattern '.*RV64.*'.
Best Regards,
Zhiwei
>
> r~
[-- Attachment #2: Type: text/html, Size: 1538 bytes --]
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
2020-05-11 18:11 ` Richard Henderson
@ 2020-05-19 12:27 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-19 12:27 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/12 2:11, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> Interesting question here: Do we really want to avoid the reserved rounding
> modes, or do we want to verify that we raise an invalid operand exception?
I think we should always generate legal instructions except explicitly
illegal instructions
with proper risu ops code.
Zhiwei
> I guess I'm fine with it either way.
>
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 8/8] riscv: Add RV64F instructions description
@ 2020-05-19 12:27 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-19 12:27 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/12 2:11, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
>> +
>> +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
>> +!constraints { $rs1 != 2 && $rm != 6 && $rm != 5 }
> Interesting question here: Do we really want to avoid the reserved rounding
> modes, or do we want to verify that we raise an invalid operand exception?
I think we should always generate legal instructions except explicitly
illegal instructions
with proper risu ops code.
Zhiwei
> I guess I'm fine with it either way.
>
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
2020-05-11 18:06 ` Richard Henderson
@ 2020-05-20 1:45 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 1:45 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/12 2:06, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +++ b/configure
>> @@ -58,6 +58,8 @@ guess_arch() {
>> ARCH="m68k"
>> elif check_define __powerpc64__ ; then
>> ARCH="ppc64"
>> + elif check_define __riscv ; then
>> + ARCH="riscv64"
>> else
>> echo "This cpu is not supported by risu. Try -h. " >&2
>> exit 1
> Why "riscv64" and not "riscv"?
>
> You can't really say more without checking __riscv_xlen.
Thanks for point it out. I will add support for RV32 next patch set.
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
@ 2020-05-20 1:45 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 1:45 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/12 2:06, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +++ b/configure
>> @@ -58,6 +58,8 @@ guess_arch() {
>> ARCH="m68k"
>> elif check_define __powerpc64__ ; then
>> ARCH="ppc64"
>> + elif check_define __riscv ; then
>> + ARCH="riscv64"
>> else
>> echo "This cpu is not supported by risu. Try -h. " >&2
>> exit 1
> Why "riscv64" and not "riscv"?
>
> You can't really say more without checking __riscv_xlen.
Thanks for point it out. I will add support for RV32 next patch set.
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
2020-05-20 1:45 ` LIU Zhiwei
@ 2020-05-20 2:28 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:28 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/20 9:45, LIU Zhiwei wrote:
>
> On 2020/5/12 2:06, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> +++ b/configure
>>> @@ -58,6 +58,8 @@ guess_arch() {
>>> ARCH="m68k"
>>> elif check_define __powerpc64__ ; then
>>> ARCH="ppc64"
>>> + elif check_define __riscv ; then
>>> + ARCH="riscv64"
>>> else
>>> echo "This cpu is not supported by risu. Try -h. " >&2
>>> exit 1
>> Why "riscv64" and not "riscv"?
>>
>> You can't really say more without checking __riscv_xlen.
> Thanks for point it out. I will add support for RV32 next patch set.
Perhaps not to support RV32, because I don't have hardware in RV32 to
support Linux.
So the next patch set will focus on the rv64gc, and add more check for
__riscv_xlen and __riscv_flen.
Zhiwei
>
>
> Zhiwei
>>
>> r~
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 6/8] riscv: Add configure script
@ 2020-05-20 2:28 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:28 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/20 9:45, LIU Zhiwei wrote:
>
> On 2020/5/12 2:06, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> +++ b/configure
>>> @@ -58,6 +58,8 @@ guess_arch() {
>>> ARCH="m68k"
>>> elif check_define __powerpc64__ ; then
>>> ARCH="ppc64"
>>> + elif check_define __riscv ; then
>>> + ARCH="riscv64"
>>> else
>>> echo "This cpu is not supported by risu. Try -h. " >&2
>>> exit 1
>> Why "riscv64" and not "riscv"?
>>
>> You can't really say more without checking __riscv_xlen.
> Thanks for point it out. I will add support for RV32 next patch set.
Perhaps not to support RV32, because I don't have hardware in RV32 to
support Linux.
So the next patch set will focus on the rv64gc, and add more check for
__riscv_xlen and __riscv_flen.
Zhiwei
>
>
> Zhiwei
>>
>> r~
>
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
2020-05-11 17:40 ` Richard Henderson
@ 2020-05-20 2:37 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:37 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/12 1:40, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> + # sequence of li rd, 0x1234567887654321
>> + #
>> + # 0: 002471b7 lui rd,0x247
>> + # 4: 8ad1819b addiw rd,rd,-1875
>> + # 8: 00c19193 slli rd,rd,0xc
>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>> + # 10: 00d19193 slli rd,rd,0xd
>> + # 14: d9518193 addi rd,rd,-619
>> + # 18: 00e19193 slli rd,rd,0xe
>> + # 1c: 32118193 addi rd,rd,801
> You don't really need to use addiw. Removing that special case would really
> simplify this.
I think I don't get it. Do you mean that the immediate will not be 64 bit?
>> +sub write_memblock_setup()
>> +{
>> + # Write code which sets up the memory block for loads and stores.
>> + # We set r0 to point to a block of 16K length
>> + # of random data, aligned to the maximum desired alignment.
>> +
>> + my $align = $MAXALIGN;
>> + my $datalen = 16384 + $align;
> risu.h:#define MEMBLOCKLEN 8192
>
> Why are you using 16384?
It's a bug.
Once I thought I should make it bigger to support vector in the future .
And even that, 8K byts is also enough, as the most bytes operates in
one instruction
is LMUL * RV_VLEN_MAX / 8 = 512 Bytes.
Zhiwei
>
> Also, typo -- you're setting r10 not r0, obviously.
>
> The rest looks fine.
>
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
@ 2020-05-20 2:37 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:37 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/12 1:40, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> + # sequence of li rd, 0x1234567887654321
>> + #
>> + # 0: 002471b7 lui rd,0x247
>> + # 4: 8ad1819b addiw rd,rd,-1875
>> + # 8: 00c19193 slli rd,rd,0xc
>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>> + # 10: 00d19193 slli rd,rd,0xd
>> + # 14: d9518193 addi rd,rd,-619
>> + # 18: 00e19193 slli rd,rd,0xe
>> + # 1c: 32118193 addi rd,rd,801
> You don't really need to use addiw. Removing that special case would really
> simplify this.
I think I don't get it. Do you mean that the immediate will not be 64 bit?
>> +sub write_memblock_setup()
>> +{
>> + # Write code which sets up the memory block for loads and stores.
>> + # We set r0 to point to a block of 16K length
>> + # of random data, aligned to the maximum desired alignment.
>> +
>> + my $align = $MAXALIGN;
>> + my $datalen = 16384 + $align;
> risu.h:#define MEMBLOCKLEN 8192
>
> Why are you using 16384?
It's a bug.
Once I thought I should make it bigger to support vector in the future .
And even that, 8K byts is also enough, as the most bytes operates in
one instruction
is LMUL * RV_VLEN_MAX / 8 = 512 Bytes.
Zhiwei
>
> Also, typo -- you're setting r10 not r0, obviously.
>
> The rest looks fine.
>
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
2020-05-11 16:39 ` Richard Henderson
@ 2020-05-20 2:41 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:41 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/12 0:39, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +LUI RISCV imm:20 rd:5 0110111 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
> I think it would be helpful to add a function for this. e.g. greg($rd) and
> gbase($rs1) (including $0). It would keep the constraints smaller, and avoid
> mistakes.
>
> These functions would go into risugen_riscv.pm.
Good idea. I will take it next patch set.
>> +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
> sp, and not gp and tp as well?
When I test the patch set, I find gp and tp will be the same in slave
and master，
so they can be used as source register.
I will check it again in next patch set test.
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
@ 2020-05-20 2:41 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 2:41 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/12 0:39, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +LUI RISCV imm:20 rd:5 0110111 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 }
> I think it would be helpful to add a function for this. e.g. greg($rd) and
> gbase($rs1) (including $0). It would keep the constraints smaller, and avoid
> mistakes.
>
> These functions would go into risugen_riscv.pm.
Good idea. I will take it next patch set.
>> +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
>> +!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
> sp, and not gp and tp as well?
When I test the patch set, I find gp and tp will be the same in slave
and master，
so they can be used as source register.
I will check it again in next patch set test.
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
2020-05-20 2:41 ` LIU Zhiwei
@ 2020-05-20 5:39 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-20 5:39 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 5/19/20 7:41 PM, LIU Zhiwei wrote:
>> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
>> sp, and not gp and tp as well?
> When I test the patch set, I find gp and tp will be the same in slave and master，
> so they can be used as source register.
Ah, try again with different builds of risu, e.g. one with -O2 and one with
-O0. I think you will find that these values are set by the linker for the image.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 1/8] riscv: Add RV64I instructions description
@ 2020-05-20 5:39 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-20 5:39 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 5/19/20 7:41 PM, LIU Zhiwei wrote:
>> Since all of sp, gp, tp are not in risu's control, why is rs1 only excluding
>> sp, and not gp and tp as well?
> When I test the patch set, I find gp and tp will be the same in slave and master，
> so they can be used as source register.
Ah, try again with different builds of risu, e.g. one with -O2 and one with
-O0. I think you will find that these values are set by the linker for the image.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
2020-05-20 2:37 ` LIU Zhiwei
@ 2020-05-20 5:41 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-20 5:41 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 5/19/20 7:37 PM, LIU Zhiwei wrote:
> On 2020/5/12 1:40, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> + # sequence of li rd, 0x1234567887654321
>>> + #
>>> + # 0: 002471b7 lui rd,0x247
>>> + # 4: 8ad1819b addiw rd,rd,-1875
>>> + # 8: 00c19193 slli rd,rd,0xc
>>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>>> + # 10: 00d19193 slli rd,rd,0xd
>>> + # 14: d9518193 addi rd,rd,-619
>>> + # 18: 00e19193 slli rd,rd,0xe
>>> + # 1c: 32118193 addi rd,rd,801
>> You don't really need to use addiw. Removing that special case would really
>> simplify this.
> I think I don't get it. Do you mean that the immediate will not be 64 bit?
Well, mostly the immediate will be small, actually. But the interface must
support 64-bit immediates.
I'm saying that for this computation,
lui
addi
slli
addi
...
is the same. You don't *have* to use addiw.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
@ 2020-05-20 5:41 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2020-05-20 5:41 UTC (permalink / raw)
To: LIU Zhiwei, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 5/19/20 7:37 PM, LIU Zhiwei wrote:
> On 2020/5/12 1:40, Richard Henderson wrote:
>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>> + # sequence of li rd, 0x1234567887654321
>>> + #
>>> + # 0: 002471b7 lui rd,0x247
>>> + # 4: 8ad1819b addiw rd,rd,-1875
>>> + # 8: 00c19193 slli rd,rd,0xc
>>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>>> + # 10: 00d19193 slli rd,rd,0xd
>>> + # 14: d9518193 addi rd,rd,-619
>>> + # 18: 00e19193 slli rd,rd,0xe
>>> + # 1c: 32118193 addi rd,rd,801
>> You don't really need to use addiw. Removing that special case would really
>> simplify this.
> I think I don't get it. Do you mean that the immediate will not be 64 bit?
Well, mostly the immediate will be small, actually. But the interface must
support 64-bit immediates.
I'm saying that for this computation,
lui
addi
slli
addi
...
is the same. You don't *have* to use addiw.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
2020-05-20 5:41 ` Richard Henderson
@ 2020-05-20 9:06 ` LIU Zhiwei
-1 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 9:06 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: qemu-riscv, qemu-devel, wxy194768, wenmeng_zhang, palmer,
alistair23, alex.bennee
On 2020/5/20 13:41, Richard Henderson wrote:
> On 5/19/20 7:37 PM, LIU Zhiwei wrote:
>> On 2020/5/12 1:40, Richard Henderson wrote:
>>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>>> + # sequence of li rd, 0x1234567887654321
>>>> + #
>>>> + # 0: 002471b7 lui rd,0x247
>>>> + # 4: 8ad1819b addiw rd,rd,-1875
>>>> + # 8: 00c19193 slli rd,rd,0xc
>>>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>>>> + # 10: 00d19193 slli rd,rd,0xd
>>>> + # 14: d9518193 addi rd,rd,-619
>>>> + # 18: 00e19193 slli rd,rd,0xe
>>>> + # 1c: 32118193 addi rd,rd,801
>>> You don't really need to use addiw. Removing that special case would really
>>> simplify this.
>> I think I don't get it. Do you mean that the immediate will not be 64 bit?
> Well, mostly the immediate will be small, actually. But the interface must
> support 64-bit immediates.
>
> I'm saying that for this computation,
>
> lui
> addi
> slli
> addi
> ...
>
> is the same. You don't *have* to use addiw.
I see addiw is not good, as it is a RV64 only instruction. I think addi
is right and better.
But I'm afraid I don't get
"Removing that special case would really
simplify this."
Do you mean I need not the decode_li function if I use addi instead of
addiw?
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [RFC PATCH 2/8] riscv: Generate payload scripts
@ 2020-05-20 9:06 ` LIU Zhiwei
0 siblings, 0 replies; 56+ messages in thread
From: LIU Zhiwei @ 2020-05-20 9:06 UTC (permalink / raw)
To: Richard Henderson, peter.maydell
Cc: alistair23, palmer, wenmeng_zhang, wxy194768, qemu-devel,
alex.bennee, qemu-riscv
On 2020/5/20 13:41, Richard Henderson wrote:
> On 5/19/20 7:37 PM, LIU Zhiwei wrote:
>> On 2020/5/12 1:40, Richard Henderson wrote:
>>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>>> + # sequence of li rd, 0x1234567887654321
>>>> + #
>>>> + # 0: 002471b7 lui rd,0x247
>>>> + # 4: 8ad1819b addiw rd,rd,-1875
>>>> + # 8: 00c19193 slli rd,rd,0xc
>>>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>>>> + # 10: 00d19193 slli rd,rd,0xd
>>>> + # 14: d9518193 addi rd,rd,-619
>>>> + # 18: 00e19193 slli rd,rd,0xe
>>>> + # 1c: 32118193 addi rd,rd,801
>>> You don't really need to use addiw. Removing that special case would really
>>> simplify this.
>> I think I don't get it. Do you mean that the immediate will not be 64 bit?
> Well, mostly the immediate will be small, actually. But the interface must
> support 64-bit immediates.
>
> I'm saying that for this computation,
>
> lui
> addi
> slli
> addi
> ...
>
> is the same. You don't *have* to use addiw.
I see addiw is not good, as it is a RV64 only instruction. I think addi
is right and better.
But I'm afraid I don't get
"Removing that special case would really
simplify this."
Do you mean I need not the decode_li function if I use addi instead of
addiw?
Zhiwei
>
> r~
^ permalink raw reply [flat|nested] 56+ messages in thread
end of thread, other threads:[~2020-05-20 9:11 UTC | newest]
Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei
2020-05-20 9:06 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 17:42 ` Richard Henderson
2020-05-11 17:42 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 18:04 ` Richard Henderson
2020-05-11 18:04 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 18:12 ` Richard Henderson
2020-05-11 18:12 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson
2020-05-11 18:11 ` Richard Henderson
2020-05-19 12:27 ` LIU Zhiwei
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-11 16:30 ` Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
2020-05-19 9:44 ` LIU Zhiwei
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