From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 054CAC433FE for ; Wed, 5 Oct 2022 14:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230236AbiJEOIW (ORCPT ); Wed, 5 Oct 2022 10:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230221AbiJEOIT (ORCPT ); Wed, 5 Oct 2022 10:08:19 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AFD978220; Wed, 5 Oct 2022 07:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664978898; x=1696514898; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=x4Mh62nAwfxY8Pita2q5xFpK6rXI3Y7xCTC5ET9xbaw=; b=XcTwy1mMYhYXdFfO2Qgg+9lKnVqZndVhZ18vjTduP9uH7FtsHn98Cg6L GnaTrTqb6cMAgsAZauttLwNoWrDtmNGZc7EjN1Oo9R0+DGamG75tnG8Il U31OTZ5GQiag9xEgMmehLNK8WCmur0jMQPlpfP/wRqs5SZa4jFkh09S7S wTyerpFd0n8nJbwpKwCPdLOa+xcOJtNyoiWLEF3upOn2hPi4XxkZ0r6QK yrMsXJBO8alhlXpT3/nUKnHVp6kJs0uWTumOcov9a88Rmk4XaXCilcmus Hc78CZ6+XJd+Pg3G0xUraWPRjKf8ap+aIYdnmF4yCMt/ZILl+0CPKlq2g A==; X-IronPort-AV: E=McAfee;i="6500,9779,10490"; a="389454804" X-IronPort-AV: E=Sophos;i="5.95,159,1661842800"; d="scan'208";a="389454804" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 07:08:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10490"; a="602018913" X-IronPort-AV: E=Sophos;i="5.95,159,1661842800"; d="scan'208";a="602018913" Received: from mghender-mobl.amr.corp.intel.com (HELO [10.209.6.185]) ([10.209.6.185]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 07:08:16 -0700 Message-ID: <715095e6-6c4e-62dd-6631-b096db2cd92c@intel.com> Date: Wed, 5 Oct 2022 07:08:15 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 10/39] x86/mm: Introduce _PAGE_COW Content-Language: en-US To: Andrew Cooper , Rick Edgecombe , "x86@kernel.org" , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , "linux-kernel@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-mm@kvack.org" , "linux-arch@vger.kernel.org" , "linux-api@vger.kernel.org" , Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Weijiang Yang , "Kirill A . Shutemov" , "joao.moreira@intel.com" , John Allen , "kcc@google.com" , "eranian@google.com" , "rppt@kernel.org" , "jamorris@linux.microsoft.com" , "dethoma@microsoft.com" Cc: Yu-cheng Yu References: <20220929222936.14584-1-rick.p.edgecombe@intel.com> <20220929222936.14584-11-rick.p.edgecombe@intel.com> <54cdad9f-b810-7966-5928-9320d970a43d@citrix.com> From: Dave Hansen In-Reply-To: <54cdad9f-b810-7966-5928-9320d970a43d@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/4/22 19:17, Andrew Cooper wrote: > On 29/09/2022 23:29, Rick Edgecombe wrote: >> From: Yu-cheng Yu >> >> There is essentially no room left in the x86 hardware PTEs on some OSes >> (not Linux). That left the hardware architects looking for a way to >> represent a new memory type (shadow stack) within the existing bits. >> They chose to repurpose a lightly-used state: Write=0,Dirty=1. > How does "Some OSes have a greater dependence on software available bits > in PTEs than Linux" sound? > >> The reason it's lightly used is that Dirty=1 is normally set _before_ a >> write. A write with a Write=0 PTE would typically only generate a fault, >> not set Dirty=1. Hardware can (rarely) both set Write=1 *and* generate the >> fault, resulting in a Dirty=0,Write=1 PTE. Hardware which supports shadow >> stacks will no longer exhibit this oddity. > Again, an interesting anecdote but not salient information here. As much as I like the sound of my own voice (and anecdotes), I agree that this is a bit oblique for the patch. Maybe this anecdote should get banished elsewhere. The changelog here could definitely get to the point faster.