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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: figlesia@xilinx.com, peter.maydell@linaro.org,
	sstabellini@kernel.org, edgar.iglesias@xilinx.com,
	sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com,
	alistair@alistair23.me, richard.henderson@linaro.org,
	frederic.konrad@adacore.com
Subject: Re: [Qemu-devel] [PATCH v1 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words
Date: Sat, 6 Oct 2018 01:09:55 +0200	[thread overview]
Message-ID: <71d17e21-7d49-989c-37c5-379e5dff966d@redhat.com> (raw)
In-Reply-To: <1538579266-8389-4-git-send-email-edgar.iglesias@gmail.com>

On 03/10/2018 17:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Use uint32_t instead of unsigned to describe 32bit descriptor words.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  hw/net/cadence_gem.c         | 42 +++++++++++++++++++++---------------------
>  include/hw/net/cadence_gem.h |  2 +-
>  2 files changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 901c173..31f3fe0 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -302,42 +302,42 @@
>  
>  #define GEM_MODID_VALUE 0x00020118
>  
> -static inline unsigned tx_desc_get_buffer(unsigned *desc)
> +static inline unsigned tx_desc_get_buffer(uint32_t *desc)
>  {
>      return desc[0];
>  }
>  
> -static inline unsigned tx_desc_get_used(unsigned *desc)
> +static inline unsigned tx_desc_get_used(uint32_t *desc)
>  {
>      return (desc[1] & DESC_1_USED) ? 1 : 0;
>  }
>  
> -static inline void tx_desc_set_used(unsigned *desc)
> +static inline void tx_desc_set_used(uint32_t *desc)
>  {
>      desc[1] |= DESC_1_USED;
>  }
>  
> -static inline unsigned tx_desc_get_wrap(unsigned *desc)
> +static inline unsigned tx_desc_get_wrap(uint32_t *desc)
>  {
>      return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
>  }
>  
> -static inline unsigned tx_desc_get_last(unsigned *desc)
> +static inline unsigned tx_desc_get_last(uint32_t *desc)
>  {
>      return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
>  }
>  
> -static inline void tx_desc_set_last(unsigned *desc)
> +static inline void tx_desc_set_last(uint32_t *desc)
>  {
>      desc[1] |= DESC_1_TX_LAST;
>  }
>  
> -static inline unsigned tx_desc_get_length(unsigned *desc)
> +static inline unsigned tx_desc_get_length(uint32_t *desc)
>  {
>      return desc[1] & DESC_1_LENGTH;
>  }
>  
> -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
> +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
>  {
>      DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
>      DB_PRINT("bufaddr: 0x%08x\n", *desc);
> @@ -347,58 +347,58 @@ static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
>      DB_PRINT("length:  %d\n", tx_desc_get_length(desc));
>  }
>  
> -static inline unsigned rx_desc_get_buffer(unsigned *desc)
> +static inline unsigned rx_desc_get_buffer(uint32_t *desc)
>  {
>      return desc[0] & ~0x3UL;
>  }
>  
> -static inline unsigned rx_desc_get_wrap(unsigned *desc)
> +static inline unsigned rx_desc_get_wrap(uint32_t *desc)
>  {
>      return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
>  }
>  
> -static inline unsigned rx_desc_get_ownership(unsigned *desc)
> +static inline unsigned rx_desc_get_ownership(uint32_t *desc)
>  {
>      return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
>  }
>  
> -static inline void rx_desc_set_ownership(unsigned *desc)
> +static inline void rx_desc_set_ownership(uint32_t *desc)
>  {
>      desc[0] |= DESC_0_RX_OWNERSHIP;
>  }
>  
> -static inline void rx_desc_set_sof(unsigned *desc)
> +static inline void rx_desc_set_sof(uint32_t *desc)
>  {
>      desc[1] |= DESC_1_RX_SOF;
>  }
>  
> -static inline void rx_desc_set_eof(unsigned *desc)
> +static inline void rx_desc_set_eof(uint32_t *desc)
>  {
>      desc[1] |= DESC_1_RX_EOF;
>  }
>  
> -static inline void rx_desc_set_length(unsigned *desc, unsigned len)
> +static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
>  {
>      desc[1] &= ~DESC_1_LENGTH;
>      desc[1] |= len;
>  }
>  
> -static inline void rx_desc_set_broadcast(unsigned *desc)
> +static inline void rx_desc_set_broadcast(uint32_t *desc)
>  {
>      desc[1] |= R_DESC_1_RX_BROADCAST;
>  }
>  
> -static inline void rx_desc_set_unicast_hash(unsigned *desc)
> +static inline void rx_desc_set_unicast_hash(uint32_t *desc)
>  {
>      desc[1] |= R_DESC_1_RX_UNICAST_HASH;
>  }
>  
> -static inline void rx_desc_set_multicast_hash(unsigned *desc)
> +static inline void rx_desc_set_multicast_hash(uint32_t *desc)
>  {
>      desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
>  }
>  
> -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
> +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
>  {
>      desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
>                          sar_idx);
> @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
>   */
>  static void gem_transmit(CadenceGEMState *s)
>  {
> -    unsigned    desc[2];
> +    uint32_t desc[2];
>      hwaddr packet_desc_addr;
>      uint8_t     tx_packet[2048];
>      uint8_t     *p;
> @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s)
>  
>              /* Last descriptor for this packet; hand the whole thing off */
>              if (tx_desc_get_last(desc)) {
> -                unsigned    desc_first[2];
> +                uint32_t desc_first[2];
>  
>                  /* Modify the 1st descriptor of this packet to be owned by
>                   * the processor.
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 35de622..633d564 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -74,7 +74,7 @@ typedef struct CadenceGEMState {
>  
>      uint8_t can_rx_state; /* Debug only */
>  
> -    unsigned rx_desc[MAX_PRIORITY_QUEUES][2];
> +    uint32_t rx_desc[MAX_PRIORITY_QUEUES][2];
>  
>      bool sar_active[4];
>  } CadenceGEMState;
> 

  parent reply	other threads:[~2018-10-05 23:10 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-03 15:07 [Qemu-devel] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC Edgar E. Iglesias
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 01/12] net: cadence_gem: Disable TSU feature bit Edgar E. Iglesias
2018-10-04 17:36   ` Alistair Francis
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 02/12] net: cadence_gem: Announce availability of priority queues Edgar E. Iglesias
2018-10-04 22:14   ` Alistair
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words Edgar E. Iglesias
2018-10-04 22:16   ` Alistair
2018-10-05 23:09   ` Philippe Mathieu-Daudé [this message]
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 04/12] net: cadence_gem: Add macro with max number of " Edgar E. Iglesias
2018-10-04 22:16   ` Alistair
2018-10-05 23:10   ` Philippe Mathieu-Daudé
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 05/12] net: cadence_gem: Add support for extended descriptors Edgar E. Iglesias
2018-10-04 22:29   ` Alistair
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion Edgar E. Iglesias
2018-10-05 22:35   ` Alistair
2018-10-05 23:14   ` Philippe Mathieu-Daudé
2018-10-08 12:26     ` Peter Maydell
2018-10-08 12:24   ` Peter Maydell
2018-10-08 19:54     ` Edgar E. Iglesias
2018-10-08 12:30   ` Peter Maydell
2018-10-08 19:55     ` Edgar E. Iglesias
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 07/12] net: cadence_gem: Implement support for 64bit descriptor addresses Edgar E. Iglesias
2018-10-05 23:12   ` Alistair
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 08/12] net: cadence_gem: Announce 64bit addressing support Edgar E. Iglesias
2018-10-04 22:32   ` Alistair
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 Edgar E. Iglesias
2018-10-08 12:41   ` Peter Maydell
2018-10-08 19:56     ` Edgar E. Iglesias
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 10/12] target/arm: Add the Cortex-A72 Edgar E. Iglesias
2018-10-08 13:10   ` Peter Maydell
2018-10-08 21:34     ` Edgar E. Iglesias
2018-10-09  9:30       ` Peter Maydell
2018-10-09 13:17         ` Edgar E. Iglesias
2018-10-09 13:40           ` Laurent Desnogues
2018-10-09 14:56             ` Edgar E. Iglesias
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 11/12] hw/arm: versal: Add a model of Xilinx Versal SoC Edgar E. Iglesias
2018-10-05 23:21   ` Philippe Mathieu-Daudé
2018-10-08 13:19   ` Peter Maydell
2018-10-08 22:25     ` Edgar E. Iglesias
2018-10-03 15:07 ` [Qemu-devel] [PATCH v1 12/12] hw/arm: versal: Add a virtual Xilinx Versal board Edgar E. Iglesias
2018-10-08 14:08 ` [Qemu-devel] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC Peter Maydell
2018-10-09 12:57   ` Edgar E. Iglesias

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