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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?B?eFU5TzFWQ2NFT2VtTVY1eXIwSXAvM0VrV3Vib2lldXplcUk4MnNyckc4Ty9t?= =?utf-8?B?NWc5ZVRGbVJ0WnlieWphOHJIaU0vQlk1Um1DakVxc3RzMnF3QkFqZzljalNO?= =?utf-8?B?YUY1MWtaTHRlajNFelFaZHdTeStacVpLZlhlNytWRmNlcS9xSWVGYVpSVEY0?= =?utf-8?B?M1JDQy9kNWRCWDVhbTkyVVpmVmhCdU5lMnh6V1V5VGxpZnlUdDQyZ29vOVQ3?= =?utf-8?B?djVPTUQ1ZHcxVFNmNlFPZmZuZXFpeXdEb2syTUQ3N09aTWJnUEpGTHJsbDhX?= =?utf-8?B?UFRPaGt5UHZMdGcwdCtyU0VJdng0dWdhdzNVOHpJaDJ0TWxvNTFPTEw0OUNs?= =?utf-8?B?enc4VHZMTzJzcWZjOW1HVXBPT1lGUXphY1VuZmRneG1VeVFETmYrWVc3eFh1?= =?utf-8?B?S3ErSEkrVTd3RUMyOXFQbEdYc3hDNlNtSmNoaUdwUThWYU9iSWtFUkhlTWxj?= =?utf-8?B?YTFGOWVKVFJXV0JNb0hqODJmbVFmcmVvb1gvZENnd3hjdjl5aVo1Rk1IVVFS?= =?utf-8?B?bk5sMXMydUtPc2dVYkJKektJUU5ieFM2MzVtUU9iY3k3VTFEOWdmYU1uUjVn?= =?utf-8?B?emFEZWRFdkMxY1FhQlhXVUxjcTF6Sk5IWkhVLzN5SlJOZUE5NTdWSTdNZGZm?= =?utf-8?B?L09RKzBNRlR0Q003YzIyeDZxRTM0U29IdkdtYmpwcEtUc1dLa3JoYUJBVWdp?= =?utf-8?B?SWFoSFAwV1BZN0xBZFNVMTFnOGdQYnR4MXJiT0N0czJHYjlRaExyNklaL3FD?= =?utf-8?B?dUI2Um52czlPZGNJUEdPcVJGOU9tNTYyOGhPTGNhczVjdHdqV3lwNUFEdjBK?= =?utf-8?B?S0Q1U05oNlV4S2RUNlF1SThJVDF5QjBOQmczcURaNWtUYlVxUWZ6MVAvRDMz?= =?utf-8?B?UnI2TktTVU04VjBGRFNxeEFHZ2h0QXEzUmlFV2kxdHJBbTZaK3ZKQklick5i?= =?utf-8?B?VERyRE91RjhRNWVWS0JiTDVsb25iVnR5YUliL1BSZjN3azFKU3ltQzNsaVZR?= =?utf-8?B?aFNnTGl2U2hzMTJ3MGxNN3UzZS9aZkpIdEIzbGNsN0lwbzRqdUJidWtmT3BH?= =?utf-8?B?UlI2QlhRWVQ0RlRRWVNZV01ZN3oyWDJLclpia1JjRUVuQXN3SVdtUnVwUlVr?= =?utf-8?B?UkUrSzJVcTVZSnRBaEtlZVk1NkRUeFRMSXR3SXMyczFwTVhJWS8xZGM1Y3Vm?= =?utf-8?B?aXl6Wit1LzEralZNUXhSNkpKaHMrNXVyWHgzTnBCVysrckhpQkc2Rzk1NlBk?= =?utf-8?B?OGxCaE5yZ0ZpVnEvY3hBU2ppd2lNczBndWNkMEQxWThmZ2VHZ25vWDYySmZi?= =?utf-8?B?QUlKRmtSWStyNnc2ZUUvcURsdFVVMzEwaVYwcjM3dTN5aG92ODkvQUJCRldH?= =?utf-8?B?NGE5RUx1V3QrVzFVVFRnb1YxeFJCRjRraFR1NUU3b1MzaDl0TytkbVJpY25j?= =?utf-8?B?SWVPMVZTZzFrY2MrNTkwamdQKzFVWEZ1YWNnU3JGeGRWVXNXdE9WM29YMXRM?= =?utf-8?B?ZDVGbDV3TkhUM2pCVitDMzdjbWRMV05nWlNqQ3NiOTEwRVJWZnMvTjAvdm5X?= =?utf-8?B?VGloMHBYcmRQZ0t3THZzWVRBbnQ5VmJneGUyMDNBb25JTlhkQlJnK2tTR3VY?= =?utf-8?B?U1dyVzFiSXhOMWN4UGtHN2JGRDNoeEM3OGpWM25rSFB0c2o0Ly9pZ001U000?= =?utf-8?B?Sk1uMUkrWCtVTEFLdkk3cmt6dEhmK282NVpqZU5SOFZTQ1BaU0V5UmtjWFJR?= =?utf-8?Q?ZoQAzVyqansTxE9dqRZzVa2LKJDAbv2AsI7VxEC?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: a3364c35-3197-43d0-65c7-08d92b10e062 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2021 06:36:13.4781 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: h+JDxLi2iXRbeZOK1d2L+QQ/XgAr+83DoeH+Wc1AbCc4zRP6HJfv0jy2XenWEwUkzDioj/a4ZRkqRw8tEwjDlg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3536 On 08.06.2021 19:05, Andrew Cooper wrote: > --- a/xen/arch/x86/tsx.c > +++ b/xen/arch/x86/tsx.c > @@ -60,6 +60,38 @@ void tsx_init(void) > */ > > /* > + * Probe for the June 2021 microcode which de-features TSX on > + * client parts. (Note - this is a subset of parts impacted by > + * the memory ordering errata.) > + * > + * RTM_ALWAYS_ABORT enumerates the new functionality, but is also > + * read as zero if TSX_FORCE_ABORT.ENABLE_RTM has been set before > + * we run. > + * > + * Undo this behaviour in Xen's view of the world. > + */ > + bool has_rtm_always_abort = cpu_has_rtm_always_abort; > + > + if ( !has_rtm_always_abort ) > + { > + uint64_t val; > + > + rdmsrl(MSR_TSX_FORCE_ABORT, val); > + > + if ( val & TSX_ENABLE_RTM ) > + has_rtm_always_abort = true; > + } > + > + /* > + * Always force RTM_ALWAYS_ABORT to be visibile, even if it > + * currently is. If the user explicitly opts to enable TSX, we'll > + * set TSX_FORCE_ABORT.ENABLE_RTM and hide RTM_ALWAYS_ABORT from > + * the general CPUID scan later. > + */ > + if ( has_rtm_always_abort ) > + setup_force_cpu_cap(X86_FEATURE_RTM_ALWAYS_ABORT); I understand the "we'll set" part, but I don't think "we'll hide" anything explicitly. Aiui it is ... > @@ -131,9 +170,36 @@ void tsx_init(void) > /* Check bottom bit only. Higher bits are various sentinels. */ > rtm_disabled = !(opt_tsx & 1); > > - lo &= ~TSX_FORCE_ABORT_RTM; > - if ( rtm_disabled ) > - lo |= TSX_FORCE_ABORT_RTM; > + lo &= ~(TSX_FORCE_ABORT_RTM | TSX_CPUID_CLEAR | TSX_ENABLE_RTM); > + > + if ( cpu_has_rtm_always_abort ) > + { > + /* > + * June 2021 microcode, on a client part with TSX de-featured: > + * - There are no mitigations for the TSX memory ordering errata. > + * - Performance counter 3 works. (I.e. it isn't being used by > + * microcode to work around the memory ordering errata.) > + * - TSX_FORCE_ABORT.FORCE_ABORT_RTM is fixed read1/write-discard. > + * - TSX_FORCE_ABORT.TSX_CPUID_CLEAR can be used to hide the > + * HLE/RTM CPUID bits. > + * - TSX_FORCE_ABORT.ENABLE_RTM may be used to opt in to > + * re-enabling RTM, at the users own risk. > + */ > + lo |= rtm_disabled ? TSX_CPUID_CLEAR : TSX_ENABLE_RTM; ... the setting of TSX_ENABLE_RTM here which, as a result, causes RTM_ALWAYS_ABORT to be clear. If that's correct, perhaps the wording in that earlier comment would better be something like "we'll set TSX_FORCE_ABORT.ENABLE_RTM and hence cause RTM_ALWAYS_ABORT to be hidden from the general CPUID scan later"? If this understanding of mine is correct, then preferably with some suitable adjustment to the comment wording Reviewed-by: Jan Beulich Also Intel recommends this for SDVs only - can we consider such a setup supported (not to speak of security supported) at all? I guess you mean to express this by saying "at their own risk" in the cmdline doc? If so, perhaps mentioning this in SUPPORT.md would be a good thing nevertheless, notwithstanding the fact that we're not really good at expressing there how command line option use affects support status. Jan