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Thu, 20 Jan 2022 15:29:53 -0800 (PST) Received: from [10.225.54.48] (unknown [10.225.54.48]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4JfzJ030Z8z1RvlN; Thu, 20 Jan 2022 15:29:52 -0800 (PST) Message-ID: <730eae0f-6d79-f84b-fe63-a1c4223d7379@opensource.wdc.com> Date: Fri, 21 Jan 2022 08:29:50 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: Content-Language: en-US To: Vitaly Wool , Myrtle Shah Cc: linux-riscv , Paul Walmsley , Palmer Dabbelt , LKML References: <20220120152828.4089364-1-gatecat@ds0.me> From: Damien Le Moal Organization: Western Digital In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022/01/21 0:37, Vitaly Wool wrote: > Hey, > > On Thu, Jan 20, 2022 at 4:30 PM Myrtle Shah wrote: >> >> These are some initial patches to bugs I found attempting to >> get a XIP kernel working on hardware: >> - 32-bit VexRiscv processor >> - kernel in SPI flash, at 0x00200000 >> - 16MB of RAM at 0x10000000 >> - MMU enabled >> >> I still have some more debugging to do, but these at least >> get the kernel as far as initialising the MMU, and I would >> appreciate feedback if anyone else is working on RISC-V XIP. > > I'll try to support you as much as I can, unfortunately I don't have > any 32-bit RISC-V around so I was rather thinking of extending the > RISC-V XIP support to 64-bit non-MMU targets. That would be great ! I am completing the buildroot patches for the K210. Got u-boot almost working for SD card boot too (fighting a problem with rootfs kernel mount on boot when using u-boot though). > For now just please keep in mind that there might be some inherent > assumptions that a target is 64 bit. > > Best regards, > Vitaly > >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Damien Le Moal Western Digital Research From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0D29C433F5 for ; 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Thu, 20 Jan 2022 15:29:53 -0800 (PST) Received: from [10.225.54.48] (unknown [10.225.54.48]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4JfzJ030Z8z1RvlN; Thu, 20 Jan 2022 15:29:52 -0800 (PST) Message-ID: <730eae0f-6d79-f84b-fe63-a1c4223d7379@opensource.wdc.com> Date: Fri, 21 Jan 2022 08:29:50 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: Content-Language: en-US To: Vitaly Wool , Myrtle Shah Cc: linux-riscv , Paul Walmsley , Palmer Dabbelt , LKML References: <20220120152828.4089364-1-gatecat@ds0.me> From: Damien Le Moal Organization: Western Digital In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220120_152958_057984_4BB6AF56 X-CRM114-Status: GOOD ( 20.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2022/01/21 0:37, Vitaly Wool wrote: > Hey, > > On Thu, Jan 20, 2022 at 4:30 PM Myrtle Shah wrote: >> >> These are some initial patches to bugs I found attempting to >> get a XIP kernel working on hardware: >> - 32-bit VexRiscv processor >> - kernel in SPI flash, at 0x00200000 >> - 16MB of RAM at 0x10000000 >> - MMU enabled >> >> I still have some more debugging to do, but these at least >> get the kernel as far as initialising the MMU, and I would >> appreciate feedback if anyone else is working on RISC-V XIP. > > I'll try to support you as much as I can, unfortunately I don't have > any 32-bit RISC-V around so I was rather thinking of extending the > RISC-V XIP support to 64-bit non-MMU targets. That would be great ! I am completing the buildroot patches for the K210. Got u-boot almost working for SD card boot too (fighting a problem with rootfs kernel mount on boot when using u-boot though). > For now just please keep in mind that there might be some inherent > assumptions that a target is 64 bit. > > Best regards, > Vitaly > >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Damien Le Moal Western Digital Research _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv