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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id da20sm2052176edb.27.2020.06.30.01.54.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 Jun 2020 01:54:23 -0700 (PDT) Subject: Re: [PATCH 5/7] hw/mips/malta: Introduce the 'malta-phys' machine To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Yunqiang Su , Aurelien Jarno , qemu-devel@nongnu.org References: <20200630081322.19146-1-f4bug@amsat.org> <20200630081322.19146-6-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <73404e5a-5c41-5f17-89d9-64cc1f943d1c@amsat.org> Date: Tue, 30 Jun 2020 10:54:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200630081322.19146-6-f4bug@amsat.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::644; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Aleksandar Rikalo , Aleksandar Markovic , Jiaxun Yang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/30/20 10:13 AM, Philippe Mathieu-Daudé wrote: > Introduce the 'malta-phys' machine, aiming to have the same > limitations as real hardware. Start by restricting the RAM > to 1GB, which is the maximum amount of memory the GT-64120A > north bridge can address. Oops wrong comment, it ended mixed from previous patch while rebasing. Corrected: "Start with 32 MB which is the default on the CoreLV, and allow up to 256 MB which is the maximum this card can accept. See MIPS Document Number: MD00051 Revision 01.07" > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/mips/malta.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/hw/mips/malta.c b/hw/mips/malta.c > index 1ca41b44db..013bf9272c 100644 > --- a/hw/mips/malta.c > +++ b/hw/mips/malta.c > @@ -1479,11 +1479,32 @@ static void malta_machine_virt_class_init(ObjectClass *oc, void *data) > mmc->max_ramsize = 2 * GiB; > } > > +static void malta_machine_phys_class_init(ObjectClass *oc, void *data) > +{ > + MachineClass *mc = MACHINE_CLASS(oc); > + MaltaMachineClass *mmc = MALTA_MACHINE_CLASS(oc); > + > + mc->desc = "MIPS Malta Core LV (physically limited as real hardware)"; > + mc->block_default_type = IF_PFLASH; > + mc->max_cpus = 1; > +#ifdef TARGET_MIPS64 > + mc->default_cpu_type = MIPS_CPU_TYPE_NAME("5Kc"); > +#else > + mc->default_cpu_type = MIPS_CPU_TYPE_NAME("4Kc"); > +#endif > + mc->default_ram_size = 32 * MiB; > + mmc->max_ramsize = 256 * MiB; /* 32 MByte PC100 SDRAM DIMMs x 4 slots */ > +}; > + > static const TypeInfo malta_machine_types[] = { > { > .name = MACHINE_TYPE_NAME("malta-virt"), > .parent = TYPE_MALTA_MACHINE, > .class_init = malta_machine_virt_class_init, > + }, { > + .name = MACHINE_TYPE_NAME("malta-phys"), > + .parent = TYPE_MALTA_MACHINE, > + .class_init = malta_machine_phys_class_init, > }, { > .name = TYPE_MALTA_MACHINE, > .parent = TYPE_MACHINE, >