From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752252AbdLFWCU (ORCPT ); Wed, 6 Dec 2017 17:02:20 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:58558 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752059AbdLFWCT (ORCPT ); Wed, 6 Dec 2017 17:02:19 -0500 Subject: Re: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS To: Eugeniy Paltsev , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "Alexey Brodkin" References: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> From: Vineet Gupta Message-ID: <734551f7-b558-b9b4-654b-9c381025c3fb@synopsys.com> Date: Wed, 6 Dec 2017 14:02:09 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.10.161.67] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/27/2017 10:56 AM, Eugeniy Paltsev wrote: > Set initial core pll output frequency on HSDK and AXS103 via > "assigned-clock-rates" property in device tree. > It will be applied at the core pll driver probing. Can you repost - CC'ing Stephen boyd and RobH ? -Vineet > > Eugeniy Paltsev (4): > ARC: [plat-hsdk]: Set initial core pll output frequency > ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code > ARC: [plat-axs103]: Set initial core pll output frequency > ARC: [plat-axs103] refactor the quad core DT quirk code > > arch/arc/boot/dts/axc003.dtsi | 3 +++ > arch/arc/boot/dts/axc003_idu.dtsi | 3 +++ > arch/arc/boot/dts/hsdk.dts | 3 +++ > arch/arc/plat-axs10x/axs10x.c | 18 ++++++++--------- > arch/arc/plat-hsdk/platform.c | 42 --------------------------------------- > 5 files changed, 17 insertions(+), 52 deletions(-) > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vineet.Gupta1@synopsys.com (Vineet Gupta) Date: Wed, 6 Dec 2017 14:02:09 -0800 Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS In-Reply-To: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> References: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> List-ID: Message-ID: <734551f7-b558-b9b4-654b-9c381025c3fb@synopsys.com> To: linux-snps-arc@lists.infradead.org On 11/27/2017 10:56 AM, Eugeniy Paltsev wrote: > Set initial core pll output frequency on HSDK and AXS103 via > "assigned-clock-rates" property in device tree. > It will be applied at the core pll driver probing. Can you repost - CC'ing Stephen boyd and RobH ? -Vineet > > Eugeniy Paltsev (4): > ARC: [plat-hsdk]: Set initial core pll output frequency > ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code > ARC: [plat-axs103]: Set initial core pll output frequency > ARC: [plat-axs103] refactor the quad core DT quirk code > > arch/arc/boot/dts/axc003.dtsi | 3 +++ > arch/arc/boot/dts/axc003_idu.dtsi | 3 +++ > arch/arc/boot/dts/hsdk.dts | 3 +++ > arch/arc/plat-axs10x/axs10x.c | 18 ++++++++--------- > arch/arc/plat-hsdk/platform.c | 42 --------------------------------------- > 5 files changed, 17 insertions(+), 52 deletions(-) >