From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCR-0004IF-0L for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aRrCN-0001Ur-QF for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:06 -0500 Received: from mail-sn1nam02on0069.outbound.protection.outlook.com ([104.47.36.69]:36016 helo=NAM02-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCN-0001Um-JZ for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:03 -0500 From: Alistair Francis Date: Fri, 5 Feb 2016 16:55:21 -0800 Message-ID: <7349b4cbd887eae0c7cc90f9e9dfc7a7f57e22b7.1454720020.git.alistair.francis@xilinx.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alindsay@codeaurora.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, cov@codeaurora.org, nathan@nathanrossi.com Signed-off-by: Aaron Lindsay Signed-off-by: Alistair Francis Tested-by: Nathan Rossi --- target-arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 164853f..8d401c6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1031,6 +1031,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .accessfn = pmreg_access, .writefn = pmovsr_write, .raw_writefn = raw_write }, + { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsr_write, + .raw_writefn = raw_write }, /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, @@ -1096,6 +1103,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, + { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .writefn = pmintenclr_write }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, -- 2.5.0