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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2022 06:30:12.3101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a5e7741-ca4d-499a-3400-08da07df9752 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4183 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If AMD Performance Monitoring Version 2 (PerfMonV2) is supported, use CPUID Fn80000022[EBX] to detect the number of Core PMCs. This offers more flexibility if the counts change across processor families. Signed-off-by: Sandipan Das --- arch/x86/events/amd/core.c | 5 +++++ arch/x86/include/asm/perf_event.h | 8 ++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index a074af97faa9..05d79afe5173 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -980,9 +980,14 @@ static int __init amd_core_pmu_init(void) /* Check for Performance Monitoring v2 support */ if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) { + int ebx = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); + /* Update PMU version for later usage */ x86_pmu.version = 2; + /* Find the number of available Core PMCs */ + x86_pmu.num_counters = EXT_PERFMON_DEBUG_NUM_CORE_PMC(ebx); + amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1; } diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 8fc1b5003713..d7dfef3e998d 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -365,6 +365,14 @@ struct pebs_xmm { u64 xmm[16*2]; /* two entries for each register */ }; +/* + * AMD Extended Performance Monitoring and Debug cpuid feature detection + */ +#define EXT_PERFMON_DEBUG_FEATURES 0x80000022 + +/* Extended Performance Monitoring and Debug EBX feature bits */ +#define EXT_PERFMON_DEBUG_NUM_CORE_PMC(ebx) ((ebx) & GENMASK(3, 0)) + /* * IBS cpuid feature detection */ -- 2.32.0