From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751406AbdFAGJM (ORCPT ); Thu, 1 Jun 2017 02:09:12 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:55123 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751195AbdFAGJI (ORCPT ); Thu, 1 Jun 2017 02:09:08 -0400 Subject: Re: [PATCH] net: ethernet: stmmac: Fix altr_tse_pcs SGMII Initialization To: , References: <1496258927-5493-1-git-send-email-thor.thayer@linux.intel.com> CC: , From: Giuseppe CAVALLARO Message-ID: <7413abda-760e-9a8f-e9ef-efab006c66a8@st.com> Date: Thu, 1 Jun 2017 08:08:57 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <1496258927-5493-1-git-send-email-thor.thayer@linux.intel.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG4NODE1.st.com (10.75.127.10) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-01_01:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/31/2017 9:28 PM, thor.thayer@linux.intel.com wrote: > From: Thor Thayer > > Fix NETDEV WATCHDOG timeout on startup by adding missing register > writes that properly setup SGMII. > > Signed-off-by: Thor Thayer Thanks a lot for this fix. Acked-by: Giuseppe Cavallaro > --- > drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c > index 489ef14..6a9c954 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c > +++ b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c > @@ -37,6 +37,7 @@ > #define TSE_PCS_CONTROL_AN_EN_MASK BIT(12) > #define TSE_PCS_CONTROL_REG 0x00 > #define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9) > +#define TSE_PCS_CTRL_AUTONEG_SGMII 0x1140 > #define TSE_PCS_IF_MODE_REG 0x28 > #define TSE_PCS_LINK_TIMER_0_REG 0x24 > #define TSE_PCS_LINK_TIMER_1_REG 0x26 > @@ -65,6 +66,7 @@ > #define TSE_PCS_SW_RESET_TIMEOUT 100 > #define TSE_PCS_USE_SGMII_AN_MASK BIT(1) > #define TSE_PCS_USE_SGMII_ENA BIT(0) > +#define TSE_PCS_IF_USE_SGMII 0x03 > > #define SGMII_ADAPTER_CTRL_REG 0x00 > #define SGMII_ADAPTER_DISABLE 0x0001 > @@ -101,7 +103,9 @@ int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs) > { > int ret = 0; > > - writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG); > + writew(TSE_PCS_IF_USE_SGMII, base + TSE_PCS_IF_MODE_REG); > + > + writew(TSE_PCS_CTRL_AUTONEG_SGMII, base + TSE_PCS_CONTROL_REG); > > writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG); > writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);