From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Zhang, Yang Z" Subject: RE: [RFC PATCH 0/3] AMD IOMMU: Share p2m table with iommu Date: Mon, 23 May 2011 21:33:33 +0800 Message-ID: <749B9D3DBF0F054390025D9EAFF47F224C3FD8B6@shsmsx501.ccr.corp.intel.com> References: <4D8C6F13.6020208@amd.com> <749B9D3DBF0F054390025D9EAFF47F224C328434@shsmsx501.ccr.corp.intel.com> <20110516082733.GO24068@whitby.uk.xensource.com> <749B9D3DBF0F054390025D9EAFF47F224C3288C0@shsmsx501.ccr.corp.intel.com> <987664A83D2D224EAE907B061CE93D5301D5BF7D34@orsmsx505.amr.corp.intel.com> <20110523105800.GC12801@whitby.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20110523105800.GC12801@whitby.uk.xensource.com> Content-Language: en-US List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Tim Deegan , "Kay, Allen M" Cc: Wei Wang , "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org Another question? Does this change ok? How to covert the p2m_type whose val= ue great than 7 to flags, like the type p2m_ram_shared which equal to 13? diff -r 51d89366c859 -r 78145a98915c xen/arch/x86/mm/p2m.c --- a/xen/arch/x86/mm/p2m.c Mon Apr 18 15:12:04 2011 +0100 +++ b/xen/arch/x86/mm/p2m.c Mon Apr 18 17:24:21 2011 +0100 @@ -80,7 +80,12 @@ { unsigned long flags; #ifdef __x86_64__ - flags =3D (unsigned long)(t & 0x3fff) << 9; + /* + * AMD IOMMU: When we share p2m table with iommu, bit 9 - bit 11 will = be + * used for iommu hardware to encode next io page level. Bit 59 - bit = 62 + * are used for iommu flags, We could not use these bits to store p2m = types. + */ + flags =3D (unsigned long)(t & 0x7f) << 12; best regards yang > -----Original Message----- > From: Tim Deegan [mailto:Tim.Deegan@citrix.com] > Sent: Monday, May 23, 2011 6:58 PM > To: Kay, Allen M > Cc: Zhang, Yang Z; Wei Wang; xen-devel@lists.xensource.com > Subject: Re: [Xen-devel] [RFC PATCH 0/3] AMD IOMMU: Share p2m table with > iommu >=20 > Hi, >=20 > At 01:51 +0100 on 21 May (1305942710), Kay, Allen M wrote: > > The common code that caused problem is the following. > > > > typedef enum { > > - p2m_invalid =3D 0, /* Nothing mapped here */ > > - p2m_ram_rw =3D 1, /* Normal read/write guest RAM */ > > + p2m_ram_rw =3D 0, /* Normal read/write guest RAM */ > > + p2m_invalid =3D 1, /* Nothing mapped here */ > > > > With the above change, guest with device direct assignment fails to > > boot. QEMU VGA displays some weird color patterns. >=20 > Unfortunately this change seems to be necessary for AMD IOMMU to share > pagetables with the p2m. I'd rather we didn't have it, because it means > empty ptes look like RAM mappings of frame 0. :( >=20 > Wei, is there any way we can reorganise the AMD IOMMU pagetables so we > can store the p2m type somewhere that's not required to be zero? If not,= I'm > inclined to revert the p2m-sharing for AMD IOMMUs, since at the very leas= t > we'd like to be able to handle types other than ram_rw (e.g. ram_ro). >=20 > In the meantime, Allen, does the attached patch make things any better fo= r > you? >=20 > Cheers, >=20 > Tim. >=20 > -- > Tim Deegan > Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. > (Company #02937203, SL9 0BG)