From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alexander Graf <agraf@csgraf.de>
Date: Sun, 24 Feb 2019 08:42:30 -0800
Subject: [U-Boot] [RFC 04/22] thunderx: add thunderx register
 definitions and misc functions
In-Reply-To: <20190222180319.32221-5-tharvey@gateworks.com>
References: <20190222180319.32221-1-tharvey@gateworks.com>
 <20190222180319.32221-5-tharvey@gateworks.com>
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On 22.02.19 19:03, Tim Harvey wrote:
> Add Cavium Thunderx common registers, structures, and helper functions
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
>  arch/arm/include/asm/arch-thunderx/thunderx.h | 300 ++++++++++++++++++
>  arch/arm/mach-thunderx/Makefile               |   2 +-
>  arch/arm/mach-thunderx/misc.c                 |  33 ++
>  3 files changed, 334 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/include/asm/arch-thunderx/thunderx.h
>  create mode 100644 arch/arm/mach-thunderx/misc.c
> 
> diff --git a/arch/arm/include/asm/arch-thunderx/thunderx.h b/arch/arm/include/asm/arch-thunderx/thunderx.h
> new file mode 100644
> index 0000000000..58f36c6cdc
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-thunderx/thunderx.h
> @@ -0,0 +1,300 @@
> +// SPDX-License-Identifier:	GPL-2.0+
> +/*
> + * Copyright (C) 2018, Cavium Inc.
> + */
> +#ifndef __THUNDERX_H__
> +#define __THUNDERX_H__
> +
> +/* Registers */
> +#define CAVM_RST_BOOT		0x87e006001600ll
> +#define CAVM_MIO_FUS_DAT2	0x87e003001410ll
> +#define CAVM_XCVX_RESET		0x87e0db000000ll
> +
> +/*
> + * Flag bits in top byte. The top byte of MIDR_EL1 is defined
> + * as ox43, the Cavium implementer code. In this number, bits
> + * 7,5,4 are defiend as zero. We use these bits to signal
> + * that revision numbers should be ignored. It isn't ideal
> + * that these are in the middle of an already defined field,
> + * but this keeps the model numbers as 32 bits
> + */
> +#define __OM_IGNORE_REVISION		0x80000000
> +#define __OM_IGNORE_MINOR_REVISION	0x20000000
> +#define __OM_IGNORE_MODEL		0x10000000
> +
> +#define CAVIUM_CN88XX_PASS1_0	0x430f0a10
> +#define CAVIUM_CN88XX_PASS1_1	0x430f0a11
> +#define CAVIUM_CN88XX_PASS2_0	0x431f0a10
> +#define CAVIUM_CN88XX_PASS2_1	0x431f0a11
> +#define CAVIUM_CN88XX_PASS2_2	0x431f0a12
> +#define CAVIUM_CN88XX		(CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_REVISION)
> +#define CAVIUM_CN88XX_PASS1_X	(CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
> +#define CAVIUM_CN88XX_PASS2_X	(CAVIUM_CN88XX_PASS2_0 | __OM_IGNORE_MINOR_REVISION)
> +
> +#define CAVIUM_CN83XX_PASS1_0	0x430f0a30
> +#define CAVIUM_CN83XX		(CAVIUM_CN83XX_PASS1_0 | __OM_IGNORE_REVISION)
> +#define CAVIUM_CN83XX_PASS1_X	(CAVIUM_CN83XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
> +
> +#define CAVIUM_CN81XX_PASS1_0	0x430f0a20
> +#define CAVIUM_CN81XX		(CAVIUM_CN81XX_PASS1_0 | __OM_IGNORE_REVISION)
> +#define CAVIUM_CN81XX_PASS1_X	(CAVIUM_CN81XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
> +
> +#define CAVIUM_CN98XX_PASS1_0	0x430f0b10
> +#define CAVIUM_CN98XX		(CAVIUM_CN98XX_PASS1_0 | __OM_IGNORE_REVISION)
> +#define CAVIUM_CN98XX_PASS1_X	(CAVIUM_CN98XX_PASS1_0 | __OM_IGNORE_MINOR_REVISION)
> +
> +/* These match entire families of chips */
> +#define CAVIUM_CN8XXX		(CAVIUM_CN88XX_PASS1_0 | __OM_IGNORE_MODEL)
> +#define CAVIUM_CN9XXX		(CAVIUM_CN98XX_PASS1_0 | __OM_IGNORE_MODEL)
> +
> +static inline uint64_t cavium_get_model(void)
> +{
> +	uint64_t result;
> +
> +	__asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
> +
> +	return result;
> +}
> +
> +/**
> + * Return non-zero if the chip matched the passed model.
> + *
> + * @param arg_model One of the CAVIUM_* constants for chip models and passes
> + * @return Non-zero if match
> + */
> +static inline int CAVIUM_IS_MODEL(uint32_t arg_model)

Usually upper case function names are reserved for #define'd ones. Could
this be lower case?


Alex