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Thu, 19 Aug 2021 12:21:59 -0700 (PDT) Received: from [192.168.3.43] ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id r17sm5410329pgu.8.2021.08.19.12.21.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Aug 2021 12:21:58 -0700 (PDT) Subject: Re: [PATCH v3 15/66] target/sh4: Implement do_unaligned_access for user-only To: Peter Maydell References: <20210818191920.390759-1-richard.henderson@linaro.org> <20210818191920.390759-16-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <755aaec3-d878-68e0-8fe9-1b82276453f7@linaro.org> Date: Thu, 19 Aug 2021 09:21:55 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.591, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers , Yoshinori Sato Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/19/21 5:46 AM, Peter Maydell wrote: > On Wed, 18 Aug 2021 at 20:26, Richard Henderson > wrote: >> >> Cc: Yoshinori Sato >> Signed-off-by: Richard Henderson >> --- >> linux-user/sh4/cpu_loop.c | 8 ++++++++ >> target/sh4/cpu.c | 2 +- >> target/sh4/op_helper.c | 3 --- >> 3 files changed, 9 insertions(+), 4 deletions(-) >> >> diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c >> index 222ed1c670..21d97250a8 100644 >> --- a/linux-user/sh4/cpu_loop.c >> +++ b/linux-user/sh4/cpu_loop.c >> @@ -71,6 +71,14 @@ void cpu_loop(CPUSH4State *env) >> info._sifields._sigfault._addr = env->tea; >> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); >> break; >> + case 0xe0: >> + case 0x100: >> + info.si_signo = TARGET_SIGBUS; >> + info.si_errno = 0; >> + info.si_code = TARGET_BUS_ADRALN; >> + info._sifields._sigfault._addr = env->tea; >> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); >> + break; >> case EXCP_ATOMIC: >> cpu_exec_step_atomic(cs); >> arch_interrupt = false; > > Doesn't this have to wait until after the later patches in the > series that implement the "actually don't worry about alignment > on most sh4 load/stores" ? Hmm. I don't think that helps. The only thing that delaying this patch would do is hit the assert in cpu_unaligned_access() due to an alignment fault occurring but not having the do_unaligned_access hook set. I think the real requirement is that the tcg/i386 patch that enforces the alignment is delayed until after all of the prctl patches. r~