From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED9D1C49EA5 for ; Thu, 24 Jun 2021 14:48:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 944F2613C3 for ; Thu, 24 Jun 2021 14:48:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 944F2613C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 058126EC0F; Thu, 24 Jun 2021 14:48:38 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74C796EC0E; Thu, 24 Jun 2021 14:48:36 +0000 (UTC) IronPort-SDR: eEqDQO7EnnSUoqms6Rk+78nmlu2fAOziEvPP0mbsi6Qo26txufQyIsCrqg4wSe9hQi8k149aLm ccXkbMJ8v7fg== X-IronPort-AV: E=McAfee;i="6200,9189,10025"; a="207522423" X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="207522423" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 07:48:35 -0700 IronPort-SDR: gyy864myTvpqgkNLq5OarZTqIb0Ns7mdFpZmMIGkOfy4tbz3Ewk0bcDFZqxr8kXOW0fQroE8J9 bL9hAVaYl4Aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="406665319" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by orsmga006.jf.intel.com with ESMTP; 24 Jun 2021 07:48:34 -0700 Received: from [10.249.129.39] (mwajdecz-MOBL.ger.corp.intel.com [10.249.129.39]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 15OEmXBr002087; Thu, 24 Jun 2021 15:48:33 +0100 Subject: Re: [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function To: Matthew Brost , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210624070516.21893-1-matthew.brost@intel.com> <20210624070516.21893-5-matthew.brost@intel.com> From: Michal Wajdeczko Message-ID: <761f2063-7fe6-518b-d05e-67f8fadb9a9c@intel.com> Date: Thu, 24 Jun 2021 16:48:32 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210624070516.21893-5-matthew.brost@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 24.06.2021 09:04, Matthew Brost wrote: > Add non blocking CTB send function, intel_guc_send_nb. GuC submission > will send CTBs in the critical path and does not need to wait for these > CTBs to complete before moving on, hence the need for this new function. > > The non-blocking CTB now must have a flow control mechanism to ensure > the buffer isn't overrun. A lazy spin wait is used as we believe the > flow control condition should be rare with a properly sized buffer. > > The function, intel_guc_send_nb, is exported in this patch but unused. > Several patches later in the series make use of this function. > > Signed-off-by: John Harrison > Signed-off-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 12 +++- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 77 +++++++++++++++++++++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 +- > 3 files changed, 82 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > index 4abc59f6f3cd..24b1df6ad4ae 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > @@ -74,7 +74,15 @@ static inline struct intel_guc *log_to_guc(struct intel_guc_log *log) > static > inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) > { > - return intel_guc_ct_send(&guc->ct, action, len, NULL, 0); > + return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0); > +} > + > +#define INTEL_GUC_SEND_NB BIT(31) hmm, this flag really belongs to intel_guc_ct_send() so it should be defined as CTB flag near that function declaration > +static > +inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len) > +{ > + return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, > + INTEL_GUC_SEND_NB); > } > > static inline int > @@ -82,7 +90,7 @@ intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, > u32 *response_buf, u32 response_buf_size) > { > return intel_guc_ct_send(&guc->ct, action, len, > - response_buf, response_buf_size); > + response_buf, response_buf_size, 0); > } > > static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > index a17215920e58..c9a65d05911f 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > @@ -3,6 +3,11 @@ > * Copyright © 2016-2019 Intel Corporation > */ > > +#include > +#include > +#include > +#include > + > #include "i915_drv.h" > #include "intel_guc_ct.h" > #include "gt/intel_gt.h" > @@ -373,7 +378,7 @@ static void write_barrier(struct intel_guc_ct *ct) > static int ct_write(struct intel_guc_ct *ct, > const u32 *action, > u32 len /* in dwords */, > - u32 fence) > + u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > struct guc_ct_buffer_desc *desc = ctb->desc; > @@ -421,9 +426,13 @@ static int ct_write(struct intel_guc_ct *ct, > FIELD_PREP(GUC_CTB_MSG_0_NUM_DWORDS, len) | > FIELD_PREP(GUC_CTB_MSG_0_FENCE, fence); > > - hxg = FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | > - FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION | > - GUC_HXG_REQUEST_MSG_0_DATA0, action[0]); > + hxg = (flags & INTEL_GUC_SEND_NB) ? > + (FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_EVENT) | > + FIELD_PREP(GUC_HXG_EVENT_MSG_0_ACTION | > + GUC_HXG_EVENT_MSG_0_DATA0, action[0])) : > + (FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | > + FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION | > + GUC_HXG_REQUEST_MSG_0_DATA0, action[0])); or as we already switched to accept and return whole HXG messages in guc_send_mmio() maybe we should do the same for CTB variant too and instead of using extra flag just let caller to prepare proper HXG header with HXG_EVENT type and then in CTB code just look at this type to make decision which code path to use note that existing callers should not be impacted, as full HXG header for the REQUEST message looks exactly the same as "action" code alone. > > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > @@ -498,6 +507,46 @@ static int wait_for_ct_request_update(struct ct_request *req, u32 *status) > return err; > } > > +static inline bool h2g_has_room(struct intel_guc_ct_buffer *ctb, u32 len_dw) > +{ > + struct guc_ct_buffer_desc *desc = ctb->desc; > + u32 head = READ_ONCE(desc->head); > + u32 space; > + > + space = CIRC_SPACE(desc->tail, head, ctb->size); > + > + return space >= len_dw; here you are returning true(1) as has room > +} > + > +static int ct_send_nb(struct intel_guc_ct *ct, > + const u32 *action, > + u32 len, > + u32 flags) > +{ > + struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > + unsigned long spin_flags; > + u32 fence; > + int ret; > + > + spin_lock_irqsave(&ctb->lock, spin_flags); > + > + ret = h2g_has_room(ctb, len + 1); but here you treat "1" it as en error and this "1" is GUC_HXG_MSG_MIN_LEN, right ? > + if (unlikely(ret)) > + goto out; > + > + fence = ct_get_next_fence(ct); > + ret = ct_write(ct, action, len, fence, flags); > + if (unlikely(ret)) > + goto out; > + > + intel_guc_notify(ct_to_guc(ct)); > + > +out: > + spin_unlock_irqrestore(&ctb->lock, spin_flags); > + > + return ret; > +} > + > static int ct_send(struct intel_guc_ct *ct, > const u32 *action, > u32 len, > @@ -505,6 +554,7 @@ static int ct_send(struct intel_guc_ct *ct, > u32 response_buf_size, > u32 *status) > { > + struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > struct ct_request request; > unsigned long flags; > u32 fence; > @@ -514,8 +564,20 @@ static int ct_send(struct intel_guc_ct *ct, > GEM_BUG_ON(!len); > GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK); > GEM_BUG_ON(!response_buf && response_buf_size); > + might_sleep(); > > + /* > + * We use a lazy spin wait loop here as we believe that if the CT > + * buffers are sized correctly the flow control condition should be > + * rare. shouldn't we at least try to log such cases with RATE_LIMITED to find out how "rare" it is, or if really unlikely just return -EBUSY as in case of non-blocking send ? > + */ > +retry: > spin_lock_irqsave(&ct->ctbs.send.lock, flags); > + if (unlikely(!h2g_has_room(ctb, len + 1))) { > + spin_unlock_irqrestore(&ct->ctbs.send.lock, flags); > + cond_resched(); > + goto retry; > + } > > fence = ct_get_next_fence(ct); > request.fence = fence; > @@ -527,7 +589,7 @@ static int ct_send(struct intel_guc_ct *ct, > list_add_tail(&request.link, &ct->requests.pending); > spin_unlock(&ct->requests.lock); > > - err = ct_write(ct, action, len, fence); > + err = ct_write(ct, action, len, fence, 0); > > spin_unlock_irqrestore(&ct->ctbs.send.lock, flags); > > @@ -569,7 +631,7 @@ static int ct_send(struct intel_guc_ct *ct, > * Command Transport (CT) buffer based GuC send function. > */ > int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len, > - u32 *response_buf, u32 response_buf_size) > + u32 *response_buf, u32 response_buf_size, u32 flags) > { > u32 status = ~0; /* undefined */ > int ret; > @@ -579,6 +641,9 @@ int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len, > return -ENODEV; > } > > + if (flags & INTEL_GUC_SEND_NB) > + return ct_send_nb(ct, action, len, flags); > + > ret = ct_send(ct, action, len, response_buf, response_buf_size, &status); > if (unlikely(ret < 0)) { > CT_ERROR(ct, "Sending action %#x failed (err=%d status=%#X)\n", > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > index 1ae2dde6db93..eb69263324ba 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > @@ -42,7 +42,6 @@ struct intel_guc_ct_buffer { > bool broken; > }; > > - > /** Top-level structure for Command Transport related data > * > * Includes a pair of CT buffers for bi-directional communication and tracking > @@ -88,7 +87,7 @@ static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct) > } > > int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len, > - u32 *response_buf, u32 response_buf_size); > + u32 *response_buf, u32 response_buf_size, u32 flags); > void intel_guc_ct_event_handler(struct intel_guc_ct *ct); > > #endif /* _INTEL_GUC_CT_H_ */ > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20F11C49EA6 for ; Thu, 24 Jun 2021 14:48:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D46CF613C3 for ; Thu, 24 Jun 2021 14:48:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D46CF613C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 867FC6EC0E; Thu, 24 Jun 2021 14:48:37 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74C796EC0E; Thu, 24 Jun 2021 14:48:36 +0000 (UTC) IronPort-SDR: eEqDQO7EnnSUoqms6Rk+78nmlu2fAOziEvPP0mbsi6Qo26txufQyIsCrqg4wSe9hQi8k149aLm ccXkbMJ8v7fg== X-IronPort-AV: E=McAfee;i="6200,9189,10025"; a="207522423" X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="207522423" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2021 07:48:35 -0700 IronPort-SDR: gyy864myTvpqgkNLq5OarZTqIb0Ns7mdFpZmMIGkOfy4tbz3Ewk0bcDFZqxr8kXOW0fQroE8J9 bL9hAVaYl4Aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,296,1616482800"; d="scan'208";a="406665319" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by orsmga006.jf.intel.com with ESMTP; 24 Jun 2021 07:48:34 -0700 Received: from [10.249.129.39] (mwajdecz-MOBL.ger.corp.intel.com [10.249.129.39]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 15OEmXBr002087; Thu, 24 Jun 2021 15:48:33 +0100 To: Matthew Brost , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210624070516.21893-1-matthew.brost@intel.com> <20210624070516.21893-5-matthew.brost@intel.com> From: Michal Wajdeczko Message-ID: <761f2063-7fe6-518b-d05e-67f8fadb9a9c@intel.com> Date: Thu, 24 Jun 2021 16:48:32 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210624070516.21893-5-matthew.brost@intel.com> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" CgpPbiAyNC4wNi4yMDIxIDA5OjA0LCBNYXR0aGV3IEJyb3N0IHdyb3RlOgo+IEFkZCBub24gYmxv Y2tpbmcgQ1RCIHNlbmQgZnVuY3Rpb24sIGludGVsX2d1Y19zZW5kX25iLiBHdUMgc3VibWlzc2lv bgo+IHdpbGwgc2VuZCBDVEJzIGluIHRoZSBjcml0aWNhbCBwYXRoIGFuZCBkb2VzIG5vdCBuZWVk IHRvIHdhaXQgZm9yIHRoZXNlCj4gQ1RCcyB0byBjb21wbGV0ZSBiZWZvcmUgbW92aW5nIG9uLCBo ZW5jZSB0aGUgbmVlZCBmb3IgdGhpcyBuZXcgZnVuY3Rpb24uCj4gCj4gVGhlIG5vbi1ibG9ja2lu ZyBDVEIgbm93IG11c3QgaGF2ZSBhIGZsb3cgY29udHJvbCBtZWNoYW5pc20gdG8gZW5zdXJlCj4g dGhlIGJ1ZmZlciBpc24ndCBvdmVycnVuLiBBIGxhenkgc3BpbiB3YWl0IGlzIHVzZWQgYXMgd2Ug YmVsaWV2ZSB0aGUKPiBmbG93IGNvbnRyb2wgY29uZGl0aW9uIHNob3VsZCBiZSByYXJlIHdpdGgg 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