Re: [Qemu-devel] [PATCH v2 1/7] target/m68k: add fscc.

[Richard Henderson <rth@twiddle.net>]

On 06/26/2017 03:03 PM, Laurent Vivier wrote:
>       case 12: /* Unordered or Less Than A || (N && !Z) */
>       case 28: /* Not Greater than or Equal A || (N && !Z) */
> -        assert(FPSR_CC_Z == (FPSR_CC_N >> 1));
> -        tmp = tcg_temp_new();
> -        tcg_gen_xori_i32(tmp, fpsr, FPSR_CC_Z);
> -        tcg_gen_shli_i32(tmp, tmp, 1);
> -        tcg_gen_ori_i32(tmp, tmp, FPSR_CC_A);
> -        tcg_gen_and_i32(tmp, tmp, fpsr);
> -        tcg_gen_andi_i32(tmp, tmp, FPSR_CC_A | FPSR_CC_N);
> -        tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
> +        g_assert(FPSR_CC_Z == (FPSR_CC_N >> 1));
> +        c->v1 = tcg_temp_new();
> +        c->g1 = 0;
> +        tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_Z);
> +        tcg_gen_shli_i32(c->v1, c->v1, 1);
> +        tcg_gen_ori_i32(c->v1, c->v1, FPSR_CC_A);
> +        tcg_gen_and_i32(c->v1, c->v1, fpsr);
> +        tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
> +        c->tcond = TCG_COND_NE;

I think you're making a mistake wrt all of these shifts, in that you haven't 
masked out the other bits in FPSR.  Eventually you'll add support for the FPSR 
quotient and the byte below CC won't be zero.

Of course, one possibility is to deconstruct FPSR into pieces so that you can 
avoid extra masking.  Whether that's worthwhile, I don't know.

Another possibility for this one is

	tcg_gen_andi_i32(tmp, fpsr, FPSR_CC_Z);
	tcg_gen_shli_i32(tmp, tmp, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
	tcg_gen_andc_i32(tmp, fpsr, tmp);
	tcg_gen_andi_i32(tmp, tmp, FPSR_CC_A | FPSR_CC_N);


r~