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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id f4-20020a170902ce8400b00178b06fea7asm4054541plg.148.2022.09.28.09.42.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 09:42:14 -0700 (PDT) Message-ID: <769e0e8a-7787-b02b-9e26-87eca955666b@linaro.org> Date: Wed, 28 Sep 2022 09:42:12 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v3 01/15] hw: encode accessing CPU index in MemTxAttrs Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Peter Xu , Jason Wang , Peter Maydell References: <20220927141504.3886314-1-alex.bennee@linaro.org> <20220927141504.3886314-2-alex.bennee@linaro.org> From: Richard Henderson In-Reply-To: <20220927141504.3886314-2-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/27/22 07:14, Alex Bennée wrote: > +/* > + * Every memory transaction comes from a specific place which defines > + * how requester_id should be handled. For CPU's the requester_id is > + * the global cpu_index which needs further processing if you need to > + * work out which socket or complex it comes from. UNSPECIFIED is the > + * default for otherwise undefined MemTxAttrs. PCI indicates the > + * requester_id is a PCI id. MACHINE indicates a machine specific > + * encoding which needs further processing to decode into its > + * constituent parts. > + */ > +typedef enum MemTxRequesterType { > + MTRT_CPU = 0, > + MTRT_UNSPECIFIED, > + MTRT_PCI, > + MTRT_MACHINE > +} MemTxRequesterType; I wonder if UNSPECIFIED should be zero, or even ILLEGAL, attempting to catch MemTxAttrs foo = { }, which is now ill-formed as it doesn't initialize .requester_id to match CPU. Perhaps a preceeding patch, should introduce #define MEMTXATTRS_CPU(cpu) ((MemTxAttrs){ }) and modify all uses of "= { }", at least under target/. > --- a/hw/misc/tz-msc.c > +++ b/hw/misc/tz-msc.c > @@ -137,11 +137,11 @@ static MemTxResult tz_msc_read(void *opaque, hwaddr addr, uint64_t *pdata, > return MEMTX_OK; > case MSCAllowSecure: > attrs.secure = 1; > - attrs.unspecified = 0; > + attrs.requester_type = MTRT_CPU; > break; > case MSCAllowNonSecure: > attrs.secure = 0; > - attrs.unspecified = 0; > + attrs.requester_type = MTRT_CPU; > break; This is surely incomplete. You can't just set "cpu" without saying where it's from. Since this device is only used by the ARMSSE machine, I would hope that attrs.unspecified should never be set before the patch, and thus MTRT_CPU should be set afterward. r~