Re: [PATCH 19/21] drm/i915: Enable skylake panel fitting using skylake shared scalers

["Konduru, Chandra" <chandra.konduru@intel.com>]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Tuesday, March 17, 2015 7:22 AM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander; Vetter, Daniel
> Subject: Re: [Intel-gfx] [PATCH 19/21] drm/i915: Enable skylake panel fitting
> using skylake shared scalers
> 
> On Sat, Mar 14, 2015 at 10:55:44PM -0700, Chandra Konduru wrote:
> > Modify skylake panel fitting implementation to use shared scalers.
> >
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> 
> Ah here's the real pfit state, and the scaler state is just readout. Still we recover
> this from the bios, I do think we need to make sure that at least the crtc scaler is
> correctly assigned. Can't we recompute the scaler state after readout to make
> sure it fits with pfit state here?
> -Daniel

Crtc scaler can be computed from hw readout. As replied earlier, will be making 
changes to update crtc scaler_id and appropriately set the scaler_users. 

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |   39 ++++++++++++++++++---------------
> -
> >  1 file changed, 21 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 8ab9624..8deebb7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4192,11 +4192,23 @@ static void skylake_pfit_enable(struct intel_crtc
> *crtc)
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	int pipe = crtc->pipe;
> > +	struct intel_crtc_scaler_state *scaler_state =
> > +		&crtc->config->scaler_state;
> >
> >  	if (crtc->config->pch_pfit.enabled) {
> > -		I915_WRITE(PS_CTL(pipe), PS_ENABLE);
> > -		I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
> > -		I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
> > +		int id;
> > +
> > +		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
> > +			DRM_ERROR("Requesting pfit without getting a scaler
> first\n");
> > +			return;
> > +		}
> > +
> > +		id = scaler_state->scaler_id;
> > +		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
> > +			scaler_state->scalers[id].mode |
> > +			scaler_state->scalers[id].filter);
> > +		I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config-
> >pch_pfit.pos);
> > +		I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config-
> >pch_pfit.size);
> >  	}
> >  }
> >
> > @@ -4664,17 +4676,7 @@ static void haswell_crtc_enable(struct drm_crtc
> > *crtc)
> >
> >  static void skylake_pfit_disable(struct intel_crtc *crtc)  {
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	int pipe = crtc->pipe;
> > -
> > -	/* To avoid upsetting the power well on haswell only disable the pfit if
> > -	 * it's in use. The hw state code will make sure we get this right. */
> > -	if (crtc->config->pch_pfit.enabled) {
> > -		I915_WRITE(PS_CTL(pipe), 0);
> > -		I915_WRITE(PS_WIN_POS(pipe), 0);
> > -		I915_WRITE(PS_WIN_SZ(pipe), 0);
> > -	}
> > +	skl_detach_scaler(&crtc->base, NULL);
> >  }
> >
> >  static void ironlake_pfit_disable(struct intel_crtc *crtc) @@
> > -7953,13 +7955,14 @@ static void skylake_get_pfit_config(struct intel_crtc
> *crtc,
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	uint32_t tmp;
> > +	int id = crtc->config->scaler_state.scaler_id;
> >
> > -	tmp = I915_READ(PS_CTL(crtc->pipe));
> > +	tmp = id >= 0 ? I915_READ(SKL_PS_CTRL(crtc->pipe, id)) : 0;
> >
> > -	if (tmp & PS_ENABLE) {
> > +	if (tmp & PS_SCALER_EN) {
> >  		pipe_config->pch_pfit.enabled = true;
> > -		pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc-
> >pipe));
> > -		pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc-
> >pipe));
> > +		pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc-
> >pipe, id));
> > +		pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc-
> >pipe,
> > +id));
> >  	}
> >  }
> >
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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