From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752363AbdHNHcs (ORCPT ); Mon, 14 Aug 2017 03:32:48 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:37215 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751978AbdHNHcr (ORCPT ); Mon, 14 Aug 2017 03:32:47 -0400 Subject: Re: [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support To: Yu Zhang , kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, xiaoguangrong@tencent.com, joro@8bytes.org References: <1502544906-1108-1-git-send-email-yu.c.zhang@linux.intel.com> From: Paolo Bonzini Message-ID: <76b17f26-be33-f54d-9023-0fafcf2b2af3@redhat.com> Date: Mon, 14 Aug 2017 09:32:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <1502544906-1108-1-git-send-email-yu.c.zhang@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/08/2017 15:35, Yu Zhang wrote: > Intel's existing processors limit the maximum linear address width to > 48 bits, and the maximum physical address width to 46 bits. And the > upcoming processors will extend maximum linear address width to 57 bits > and maximum physical address width can go upto 52 bits in practical. > > With linear address width greater than 48, a new paging mode in IA-32e > is introduced - 5 level paging(also known as LA57). And to support VMs > with this feature, KVM MMU code need to be extended. > > And to achieve this, this patchset: > 1> leverages 2 qemu parameters: +la57 and phys-bits to expose wider linear > address width and physical address width to the VM; > 2> extends shadow logic to construct 5 level shadow page for VMs running > in LA57 mode; > 3> extends ept logic to construct 5 level ept table for VMs whose maximum > physical width exceeds 48 bits. Thanks, this looks good. I only had a few suggestions in my reply to patch 3. Paolo