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Thu, 23 Mar 2023 06:25:58 +0000 Received: from BY5PR11MB4500.namprd11.prod.outlook.com ([fe80::68a4:ef95:6726:3fc5]) by BY5PR11MB4500.namprd11.prod.outlook.com ([fe80::68a4:ef95:6726:3fc5%4]) with mapi id 15.20.6178.038; Thu, 23 Mar 2023 06:25:58 +0000 Message-ID: <77f5c495-f065-a559-4549-5d2e08a14642@intel.com> Date: Thu, 23 Mar 2023 14:25:46 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx Content-Language: en-US From: "Wu, Fei" To: LIU Zhiwei , , CC: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Christoph Muellner , Richard Henderson References: <20230323024412.324085-1-fei2.wu@intel.com> <20230323024412.324085-2-fei2.wu@intel.com> <9423db2e-257f-016d-b404-17d8e5adc0ac@linux.alibaba.com> <7db6d615-5ddc-5e1b-1d3c-a85c22e6af74@intel.com> In-Reply-To: <7db6d615-5ddc-5e1b-1d3c-a85c22e6af74@intel.com> Content-Type: text/plain; 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envelope-from=fei2.wu@intel.com; helo=mga06.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/23/2023 2:00 PM, Wu, Fei wrote: > On 3/23/2023 1:37 PM, LIU Zhiwei wrote: >> >> On 2023/3/23 10:44, Fei Wu wrote: >>> Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, >>> this assumption won't last as we are about to add more mmu_idx. >> For patch set has more than 1 patch, usually add a cover letter. > > This is cover letter: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg950849.html > > I added scripts/get_maintainer.pl to .git/config, it couldn't find out > the maintainers for the cover letter, so I added the mail lists to "To" > manually. > >>> >>> Signed-off-by: Fei Wu >>> --- >>>   target/riscv/cpu.h                             | 1 - >>>   target/riscv/cpu_helper.c                      | 2 +- >>>   target/riscv/insn_trans/trans_privileged.c.inc | 2 +- >>>   target/riscv/insn_trans/trans_xthead.c.inc     | 7 +------ >>>   target/riscv/translate.c                       | 3 +++ >>>   5 files changed, 6 insertions(+), 9 deletions(-) >>> >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>> index 638e47c75a..66f7e3d1ba 100644 >>> --- a/target/riscv/cpu.h >>> +++ b/target/riscv/cpu.h >>> @@ -623,7 +623,6 @@ G_NORETURN void >>> riscv_raise_exception(CPURISCVState *env, >>>   target_ulong riscv_cpu_get_fflags(CPURISCVState *env); >>>   void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); >>>   -#define TB_FLAGS_PRIV_MMU_MASK                3 >>>   #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2) >>>   #define TB_FLAGS_MSTATUS_FS MSTATUS_FS >>>   #define TB_FLAGS_MSTATUS_VS MSTATUS_VS >>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c >>> index f88c503cf4..76e1b0100e 100644 >>> --- a/target/riscv/cpu_helper.c >>> +++ b/target/riscv/cpu_helper.c >>> @@ -762,7 +762,7 @@ static int get_physical_address(CPURISCVState >>> *env, hwaddr *physical, >>>        * (riscv_cpu_do_interrupt) is correct */ >>>       MemTxResult res; >>>       MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; >>> -    int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; >>> +    int mode = env->priv; >>>       bool use_background = false; >>>       hwaddr ppn; >>>       RISCVCPU *cpu = env_archcpu(env); >>> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc >>> b/target/riscv/insn_trans/trans_privileged.c.inc >>> index 59501b2780..9305b18299 100644 >>> --- a/target/riscv/insn_trans/trans_privileged.c.inc >>> +++ b/target/riscv/insn_trans/trans_privileged.c.inc >>> @@ -52,7 +52,7 @@ static bool trans_ebreak(DisasContext *ctx, >>> arg_ebreak *a) >>>        * that no exception will be raised when fetching them. >>>        */ >>>   -    if (semihosting_enabled(ctx->mem_idx < PRV_S) && >>> +    if (semihosting_enabled(ctx->priv < PRV_S) && >>>           (pre_addr & TARGET_PAGE_MASK) == (post_addr & >>> TARGET_PAGE_MASK)) { >>>           pre    = opcode_at(&ctx->base, pre_addr); >>>           ebreak = opcode_at(&ctx->base, ebreak_addr); >>> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc >>> b/target/riscv/insn_trans/trans_xthead.c.inc >>> index df504c3f2c..adfb53cb4c 100644 >>> --- a/target/riscv/insn_trans/trans_xthead.c.inc >>> +++ b/target/riscv/insn_trans/trans_xthead.c.inc >>> @@ -265,12 +265,7 @@ static bool trans_th_tst(DisasContext *ctx, >>> arg_th_tst *a) >>>     static inline int priv_level(DisasContext *ctx) >>>   { >>> -#ifdef CONFIG_USER_ONLY >>> -    return PRV_U; >>> -#else >>> -     /* Priv level is part of mem_idx. */ >>> -    return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; >>> -#endif >>> +    return ctx->priv; >>>   } >>>     /* Test if priv level is M, S, or U (cannot fail). */ >>> diff --git a/target/riscv/translate.c b/target/riscv/translate.c >>> index 0ee8ee147d..e8880f9423 100644 >>> --- a/target/riscv/translate.c >>> +++ b/target/riscv/translate.c >>> @@ -69,6 +69,7 @@ typedef struct DisasContext { >>>       uint32_t mstatus_hs_fs; >>>       uint32_t mstatus_hs_vs; >>>       uint32_t mem_idx; >>> +    uint32_t priv; >>>       /* Remember the rounding mode encoded in the previous fp >>> instruction, >>>          which we have already installed into env->fp_status.  Or -1 for >>>          no previous fp instruction.  Note that we exit the TB when >>> writing >>> @@ -1162,8 +1163,10 @@ static void >>> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) >>>       } else { >>>           ctx->virt_enabled = false; >>>       } >>> +    ctx->priv = env->priv; >> >> This is not right. You should put env->priv into tb flags before you use >> it in translation. >> > I see some other env usages in this function, when will env->priv and > tb_flags.priv mismatch (assume we have recorded priv in tb_flags)? > I looks that they are from the same source. cpu_exec_loop cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); flags |= cpu_mmu_index(env, 0); // <-- generate flags from env tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); tb->flags = flags; setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &ti); gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc); DisasContext dc; translator_loop(cpu, tb, ..., &dc.base); ops->init_disas_context(db, cpu); // riscv_tr_ ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); tcg_gen_code(tcg_ctx, tb, pc); Thanks, Fei. > Thanks, > Fei. > >> Zhiwei >> >>>   #else >>>       ctx->virt_enabled = false; >>> +    ctx->priv = PRV_U; >>>   #endif >>>       ctx->misa_ext = env->misa_ext; >>>       ctx->frm = -1;  /* unknown rounding mode */ >