* [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched
@ 2021-11-09 10:25 João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
` (5 more replies)
0 siblings, 6 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-09 10:25 UTC (permalink / raw)
To: palmer, paul.walmsley, aou; +Cc: atish.patra, anup.patel, linux-riscv
This series of patches introduces support for the RISC-V PMU identification and raw events matching between perf and the PMU.
The HiFive Unmatched board can now use all the counters with named events.
The work in these patches is completelly and directly dependent on the proposed SBI PMU patch [4], by Atish Patra.
This series has been tested in the HiFive Unmatched board.
OpenSBI[1] and U-Boot[2] patches are required to test it on the board, alongside with the series of patches that introduce RISC-V Perf support with the SBI PMU and sscofpmf extension [3-4].
The U-Boot fu740 dts [5] must be updated, may be fixed in future U-BOOT versions, with the events that will be tested, this comprehends changes to the riscv,raw-event-to-mhpmcounters entry. Also, an OpenSBI patch [6] proposes bitfield awareness for the DT raw-events, this will simplify, and improve, events description in the DT file.
Here is the output of perf list and perf stat with all the available unmatched events monitoring a stress-ng trignometric stressor.
HiFive Unmatched:
=================
perf list pmu
instructions:
atomic_memory_retired
[Atomic memory operation retired]
conditional_branch_retired
[Conditional branch retired]
exception_taken
[Exception taken]
fp_addition_retired
[Floating-point addition retired]
fp_div_sqrt_retired
[Floating-point division or square-root retired]
fp_fusedmadd_retired
[Floating-point fused multiply-add retired]
fp_load_retired
[Floating-point load instruction retired]
fp_multiplication_retired
[Floating-point multiplication retired]
fp_store_retired
[Floating-point store instruction retired]
integer_arithmetic_retired
[Integer arithmetic instruction retired]
integer_division_retired
[Integer division instruction retired]
integer_load_retired
[Integer load instruction retired]
integer_multiplication_retired
[Integer multiplication instruction retired]
integer_store_retired
[Integer store instruction retired]
jal_instruction_retired
[JAL instruction retired]
jalr_instruction_retired
[JALR instruction retired]
other_fp_retired
[Other floating-point instruction retired]
system_instruction_retired
[System instruction retired]
memory:
data_tlb_miss
[Data TLB miss]
dcache_miss_mmio_accesses
[Data cache miss or memory-mapped I/O access]
dcache_writeback
[Data cache write-back]
icache_retired
[Instruction cache miss]
inst_tlb_miss
[Instruction TLB miss]
utlb_miss
[UTLB miss]
microarch:
addressgen_interlock
[Address-generation interlock]
branch_direction_misprediction
[Branch direction misprediction]
branch_target_misprediction
[Branch/jump target misprediction]
csr_read_interlock
[CSR read interlock]
dcache_dtim_busy
[Data cache/DTIM busy]
fp_interlock
[Floating-point interlock]
icache_itim_busy
[Instruction cache/ITIM busy]
integer_multiplication_interlock
[Integer multiplication interlock]
longlat_interlock
[Long-latency interlock]
pipe_flush_csr_write
[Pipeline flush from CSR write]
pipe_flush_other_event
[Pipeline flush from other event]
perf stat -eexception_taken,integer_load_retired,integer_store_retired,atomic_memory_retired,system_instruction_retired,integer_arithmetic_retired,conditional_branch_retired,jal_instruction_retired,jalr_instruction_retired,integer_multiplication_retired,integer_division_retired,fp_load_retired,fp_store_retired,fp_addition_retired,fp_multiplication_retired,fp_fusedmadd_retired,fp_div_sqrt_retired,other_fp_retired,data_tlb_miss,dcache_miss_mmio_accesses,dcache_writeback,icache_retired,inst_tlb_miss,utlb_miss,addressgen_interlock,longlat_interlock,csr_read_interlock,icache_itim_busy,dcache_dtim_busy,branch_direction_misprediction,branch_target_misprediction,pipe_flush_csr_write,pipe_flush_other_event,integer_multiplication_interlock,fp_interlock stress-ng --cpu 1 --cpu-method trig -t 60s
stress-ng: info: [500] setting to a 60 second run per stressor
stress-ng: info: [500] dispatching hogs: 1 cpu
stress-ng: info: [500] successful run completed in 60.02s (1 min, 0.02 secs)
Performance counter stats for 'stress-ng --cpu 1 --cpu-method trig -t 60s':
233185 exception_taken (5.72%)
5010843878 integer_load_retired (5.73%)
4437123760 integer_store_retired (5.73%)
875636 atomic_memory_retired (5.72%)
787401517 system_instruction_retired (5.73%)
58176497169 integer_arithmetic_retired (5.74%)
9689155944 conditional_branch_retired (5.73%)
2141143732 jal_instruction_retired (5.72%)
624939326 jalr_instruction_retired (5.72%)
1900272300 integer_multiplication_retired (5.72%)
29231344 integer_division_retired (5.72%)
1672274835 fp_load_retired (5.73%)
592215149 fp_store_retired (5.73%)
13592616 fp_addition_retired (5.73%)
13597374 fp_multiplication_retired (5.72%)
1331957808 fp_fusedmadd_retired (5.72%)
592410829 fp_div_sqrt_retired (5.72%)
227334317 other_fp_retired (5.72%)
95772283 data_tlb_miss (5.72%)
6291088 dcache_miss_mmio_accesses (5.72%)
55591 dcache_writeback (5.72%)
47394708 icache_retired (5.72%)
62778259 inst_tlb_miss (5.72%)
10159938 utlb_miss (5.72%)
424446212 addressgen_interlock (5.72%)
849061809 longlat_interlock (5.72%)
0 csr_read_interlock (5.71%)
16924613138 icache_itim_busy (5.71%)
204163844 dcache_dtim_busy (5.70%)
175163620 branch_direction_misprediction (5.72%)
202874026 branch_target_misprediction (5.71%)
433228932 pipe_flush_csr_write (5.71%)
0 pipe_flush_other_event (5.71%)
429384915 integer_multiplication_interlock (5.71%)
8635530214 fp_interlock (5.71%)
60.044837787 seconds time elapsed
60.001431000 seconds user
0.033660000 seconds sys
[1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
[2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
[3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
[4] http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
[5] https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
[6] https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
This work was developed at INESC-ID, Instituto Superior Técnico, Universidade de Lisboa.
João Mário Domingos (4):
RISC-V: Create unique identification for SoC PMU
RISC-V: Support CPUID for risc-v in perf
RISC-V: Added generic pmu-events mapfile
RISC-V: Added HiFive Unmatched PMU events
arch/riscv/kernel/sbi.c | 3 +
drivers/perf/riscv_pmu.c | 18 ++++
drivers/perf/riscv_pmu_sbi.c | 46 ++++++++++
tools/perf/arch/riscv/util/Build | 1 +
tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
.../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
.../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++
10 files changed, 350 insertions(+)
create mode 100644 tools/perf/arch/riscv/util/header.c
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
--
2.17.1
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^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/4] RISC-V: Create unique identification for SoC PMU
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
@ 2021-11-09 10:25 ` João Mário Domingos
2021-11-15 8:23 ` Nikita Shubin
2021-11-09 10:25 ` [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
` (4 subsequent siblings)
5 siblings, 1 reply; 23+ messages in thread
From: João Mário Domingos @ 2021-11-09 10:25 UTC (permalink / raw)
To: palmer, paul.walmsley, aou; +Cc: atish.patra, anup.patel, linux-riscv
The SBI PMU platform driver did not provide any identification for
perf events matching. This patch introduces a new sysfs file inside the
platform device (soc:pmu/id) for pmu identification.
The identification is a 64-bit value generated as:
[63-32]: mvendorid;
[31]: marchid[MSB];
[30-16]: marchid[15-0];
[15-0]: mimpid[15MSBs];
The CSRs are detailed in the RISC-V privileged spec [1].
The marchid is split in MSB + 15LSBs, due to the MSB being used for
open-source architecture identification.
[1] https://github.com/riscv/riscv-isa-manual
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
arch/riscv/kernel/sbi.c | 3 +++
drivers/perf/riscv_pmu_sbi.c | 46 ++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 7402a417f38e..4e4f5671b864 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -551,16 +551,19 @@ long sbi_get_mvendorid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
}
+EXPORT_SYMBOL(sbi_get_mvendorid);
long sbi_get_marchid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
}
+EXPORT_SYMBOL(sbi_get_marchid);
long sbi_get_mimpid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
}
+EXPORT_SYMBOL(sbi_get_mimpid);
static void sbi_send_cpumask_ipi(const struct cpumask *target)
{
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 7a68dfa89f6f..f913d8ddfe73 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -236,6 +236,15 @@ static const struct pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
},
};
+static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
+
+static struct attribute *pmu_sbi_attrs[] = {
+ &dev_attr_id.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(pmu_sbi);
+
static int pmu_sbi_ctr_get_width(int idx)
{
return pmu_ctr_list[idx].width;
@@ -642,6 +651,36 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
return 0;
}
+static uint64_t pmu_sbi_get_pmu_id(void)
+{
+ union sbi_pmu_id {
+ uint64_t value;
+ struct {
+ uint16_t imp:16;
+ uint16_t arch:16;
+ uint32_t vendor:32;
+ };
+ }pmuid;
+
+ pmuid.value = 0;
+ pmuid.vendor = (uint32_t) sbi_get_mvendorid();
+ pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) | ( sbi_get_marchid() & 0x7FFF );
+ pmuid.imp = (sbi_get_mimpid() >> 16);
+
+ return pmuid.value;
+}
+
+static ssize_t pmu_sbi_id_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len;
+ len = sprintf(buf, "0x%lx\n", pmu_sbi_get_pmu_id());
+ if (len <= 0)
+ dev_err(dev, "mydrv: Invalid sprintf len: %dn", len);
+
+ return len;
+}
+
static int pmu_sbi_device_probe(struct platform_device *pdev)
{
struct riscv_pmu *pmu = NULL;
@@ -680,6 +719,13 @@ static int pmu_sbi_device_probe(struct platform_device *pdev)
pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
pmu->ctr_read = pmu_sbi_ctr_read;
+ ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group);
+ if (ret) {
+ dev_err(&pdev->dev, "sysfs creation failed\n");
+ return ret;
+ }
+ pdev->dev.groups = pmu_sbi_groups;
+
ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
if (ret)
return ret;
--
2.17.1
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
@ 2021-11-09 10:25 ` João Mário Domingos
2021-11-09 10:25 ` [PATCH 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
` (3 subsequent siblings)
5 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-09 10:25 UTC (permalink / raw)
To: palmer, paul.walmsley, aou; +Cc: atish.patra, anup.patel, linux-riscv
This patch creates the header.c file for the risc-v architecture and introduces support for
PMU identification through sysfs.
It is now possible to configure pmu-events in risc-v.
Depends on patch [1], that introduces the id sysfs file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
drivers/perf/riscv_pmu.c | 18 ++++++++
tools/perf/arch/riscv/util/Build | 1 +
| 66 +++++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
create mode 100644 tools/perf/arch/riscv/util/header.c
diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index 0c853e23f679..3752ffd4edaf 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -17,6 +17,23 @@
#include <asm/sbi.h>
+PMU_FORMAT_ATTR(event, "config:0-63");
+
+static struct attribute *riscv_arch_formats_attr[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static struct attribute_group riscv_pmu_format_group = {
+ .name = "format",
+ .attrs = riscv_arch_formats_attr,
+};
+
+static const struct attribute_group *riscv_pmu_attr_groups[] = {
+ &riscv_pmu_format_group,
+ NULL,
+};
+
static unsigned long csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num, __val) {\
@@ -314,6 +331,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
cpuc->events[i] = NULL;
}
pmu->pmu = (struct pmu) {
+ .attr_groups = riscv_pmu_attr_groups,
.event_init = riscv_pmu_event_init,
.add = riscv_pmu_add,
.del = riscv_pmu_del,
diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
index 7d3050134ae0..603dbb5ae4dc 100644
--- a/tools/perf/arch/riscv/util/Build
+++ b/tools/perf/arch/riscv/util/Build
@@ -1,4 +1,5 @@
perf-y += perf_regs.o
+perf-y += header.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
--git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c
new file mode 100644
index 000000000000..ef739ae36d48
--- /dev/null
+++ b/tools/perf/arch/riscv/util/header.c
@@ -0,0 +1,66 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <api/fs/fs.h>
+#include <errno.h>
+#include "../../util/debug.h"
+#include "../../util/header.h"
+
+#define STR_LEN 1024
+#define ID_SIZE 64
+
+static int _get_cpuid(char *buf, size_t sz)
+{
+ const char *sysfs = sysfs__mountpoint();
+ u64 id = 0;
+ char path[PATH_MAX];
+ FILE *file;
+
+ if (!sysfs || sz < ID_SIZE)
+ return EINVAL;
+
+ scnprintf(path, PATH_MAX, "%s/devices/platform/soc/soc:pmu/id",
+ sysfs);
+
+ file = fopen(path, "r");
+ if (!file) {
+ pr_debug("fopen failed for file %s\n", path);
+ return EINVAL;
+ }
+ if (!fgets(buf, ID_SIZE, file)) {
+ fclose(file);
+ return EINVAL;
+ }
+
+ fclose(file);
+
+ /*Check if value is numeric and remove special characters*/
+ id = strtoul(buf, NULL, 16);
+ if (!id)
+ return EINVAL;
+ scnprintf(buf, ID_SIZE, "0x%lx", id);
+
+ return 0;
+}
+
+char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
+{
+ char *buf = NULL;
+ int res;
+
+ if (!pmu)
+ return NULL;
+
+ buf = malloc(ID_SIZE);
+ if (!buf)
+ return NULL;
+
+ /* read id */
+ res = _get_cpuid(buf, ID_SIZE);
+ if (res) {
+ pr_err("failed to get cpuid string for PMU %s\n", pmu->name);
+ free(buf);
+ buf = NULL;
+ }
+
+ return buf;
+}
\ No newline at end of file
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/4] RISC-V: Added generic pmu-events mapfile
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-09 10:25 ` [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
@ 2021-11-09 10:25 ` João Mário Domingos
2021-11-09 10:25 ` [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
` (2 subsequent siblings)
5 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-09 10:25 UTC (permalink / raw)
To: palmer, paul.walmsley, aou; +Cc: atish.patra, anup.patel, linux-riscv
The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++
.../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++
2 files changed, 34 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
new file mode 100644
index 000000000000..6a1ab4209334
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+# MIDR,Version,JSON/file/pathname,Type
+#
+# where
+# MIDR Processor version
+# Variant[23:20] and Revision [3:0] should be zero.
+# Version could be used to track version of of JSON file
+# but currently unused.
+# JSON/file/pathname is the path to JSON file, relative
+# to tools/perf/pmu-events/arch/riscv/.
+# Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
new file mode 100644
index 000000000000..013e50efad99
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
@@ -0,0 +1,20 @@
+[
+ {
+ "PublicDescription": "CPU Cycles",
+ "EventCode": "0x00",
+ "EventName": "riscv_cycles",
+ "BriefDescription": "CPU cycles RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Time",
+ "EventCode": "0x01",
+ "EventName": "riscv_time",
+ "BriefDescription": "CPU time RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Instructions",
+ "EventCode": "0x02",
+ "EventName": "riscv_instret",
+ "BriefDescription": "CPU retired instructions RISC-V generic counter"
+ }
+]
\ No newline at end of file
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
` (2 preceding siblings ...)
2021-11-09 10:25 ` [PATCH 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
@ 2021-11-09 10:25 ` João Mário Domingos
2021-11-10 13:55 ` [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
5 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-09 10:25 UTC (permalink / raw)
To: palmer, paul.walmsley, aou; +Cc: atish.patra, anup.patel, linux-riscv
This patch contains all the available events for the HiFive Unmatched performance monitoring unit.
Depends on patch [3], for the base mapfile.csv file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++
4 files changed, 182 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 6a1ab4209334..9e540938a8cf 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -12,3 +12,4 @@
#
#
#Family-model,Version,Filename,EventType
+0x48980072018,v1,sifive/u74,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
new file mode 100644
index 000000000000..5eab718c9256
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
@@ -0,0 +1,92 @@
+[
+ {
+ "EventName": "EXCEPTION_TAKEN",
+ "EventCode": "0x0000100",
+ "BriefDescription": "Exception taken"
+ },
+ {
+ "EventName": "INTEGER_LOAD_RETIRED",
+ "EventCode": "0x0000200",
+ "BriefDescription": "Integer load instruction retired"
+ },
+ {
+ "EventName": "INTEGER_STORE_RETIRED",
+ "EventCode": "0x0000400",
+ "BriefDescription": "Integer store instruction retired"
+ },
+ {
+ "EventName": "ATOMIC_MEMORY_RETIRED",
+ "EventCode": "0x0000800",
+ "BriefDescription": "Atomic memory operation retired"
+ },
+ {
+ "EventName": "SYSTEM_INSTRUCTION_RETIRED",
+ "EventCode": "0x0001000",
+ "BriefDescription": "System instruction retired"
+ },
+ {
+ "EventName": "INTEGER_ARITHMETIC_RETIRED",
+ "EventCode": "0x0002000",
+ "BriefDescription": "Integer arithmetic instruction retired"
+ },
+ {
+ "EventName": "CONDITIONAL_BRANCH_RETIRED",
+ "EventCode": "0x0004000",
+ "BriefDescription": "Conditional branch retired"
+ },
+ {
+ "EventName": "JAL_INSTRUCTION_RETIRED",
+ "EventCode": "0x0008000",
+ "BriefDescription": "JAL instruction retired"
+ },
+ {
+ "EventName": "JALR_INSTRUCTION_RETIRED",
+ "EventCode": "0x0010000",
+ "BriefDescription": "JALR instruction retired"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0020000",
+ "BriefDescription": "Integer multiplication instruction retired"
+ },
+ {
+ "EventName": "INTEGER_DIVISION_RETIRED",
+ "EventCode": "0x0040000",
+ "BriefDescription": "Integer division instruction retired"
+ },
+ {
+ "EventName": "FP_LOAD_RETIRED",
+ "EventCode": "0x0080000",
+ "BriefDescription": "Floating-point load instruction retired"
+ },
+ {
+ "EventName": "FP_STORE_RETIRED",
+ "EventCode": "0x0100000",
+ "BriefDescription": "Floating-point store instruction retired"
+ },
+ {
+ "EventName": "FP_ADDITION_RETIRED",
+ "EventCode": "0x0200000",
+ "BriefDescription": "Floating-point addition retired"
+ },
+ {
+ "EventName": "FP_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0400000",
+ "BriefDescription": "Floating-point multiplication retired"
+ },
+ {
+ "EventName": "FP_FUSEDMADD_RETIRED",
+ "EventCode": "0x0800000",
+ "BriefDescription": "Floating-point fused multiply-add retired"
+ },
+ {
+ "EventName": "FP_DIV_SQRT_RETIRED",
+ "EventCode": "0x1000000",
+ "BriefDescription": "Floating-point division or square-root retired"
+ },
+ {
+ "EventName": "OTHER_FP_RETIRED",
+ "EventCode": "0x2000000",
+ "BriefDescription": "Other floating-point instruction retired"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
new file mode 100644
index 000000000000..be1a46312ac3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
@@ -0,0 +1,32 @@
+[
+ {
+ "EventName": "ICACHE_RETIRED",
+ "EventCode": "0x0000102",
+ "BriefDescription": "Instruction cache miss"
+ },
+ {
+ "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+ "EventCode": "0x0000202",
+ "BriefDescription": "Data cache miss or memory-mapped I/O access"
+ },
+ {
+ "EventName": "DCACHE_WRITEBACK",
+ "EventCode": "0x0000402",
+ "BriefDescription": "Data cache write-back"
+ },
+ {
+ "EventName": "INST_TLB_MISS",
+ "EventCode": "0x0000802",
+ "BriefDescription": "Instruction TLB miss"
+ },
+ {
+ "EventName": "DATA_TLB_MISS",
+ "EventCode": "0x0001002",
+ "BriefDescription": "Data TLB miss"
+ },
+ {
+ "EventName": "UTLB_MISS",
+ "EventCode": "0x0002002",
+ "BriefDescription": "UTLB miss"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
new file mode 100644
index 000000000000..50ffa55418cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x0000101",
+ "BriefDescription": "Address-generation interlock"
+ },
+ {
+ "EventName": "LONGLAT_INTERLOCK",
+ "EventCode": "0x0000201",
+ "BriefDescription": "Long-latency interlock"
+ },
+ {
+ "EventName": "CSR_READ_INTERLOCK",
+ "EventCode": "0x0000401",
+ "BriefDescription": "CSR read interlock"
+ },
+ {
+ "EventName": "ICACHE_ITIM_BUSY",
+ "EventCode": "0x0000801",
+ "BriefDescription": "Instruction cache/ITIM busy"
+ },
+ {
+ "EventName": "DCACHE_DTIM_BUSY",
+ "EventCode": "0x0001001",
+ "BriefDescription": "Data cache/DTIM busy"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x0002001",
+ "BriefDescription": "Branch direction misprediction"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x0004001",
+ "BriefDescription": "Branch/jump target misprediction"
+ },
+ {
+ "EventName": "PIPE_FLUSH_CSR_WRITE",
+ "EventCode": "0x0008001",
+ "BriefDescription": "Pipeline flush from CSR write"
+ },
+ {
+ "EventName": "PIPE_FLUSH_OTHER_EVENT",
+ "EventCode": "0x0010001",
+ "BriefDescription": "Pipeline flush from other event"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+ "EventCode": "0x0020001",
+ "BriefDescription": "Integer multiplication interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x0040001",
+ "BriefDescription": "Floating-point interlock"
+ }
+]
\ No newline at end of file
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
` (3 preceding siblings ...)
2021-11-09 10:25 ` [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
@ 2021-11-10 13:55 ` Nikita Shubin
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
5 siblings, 0 replies; 23+ messages in thread
From: Nikita Shubin @ 2021-11-10 13:55 UTC (permalink / raw)
To: linux-riscv
Hello Mario!
On Tue, 9 Nov 2021 10:25:51 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> This series of patches introduces support for the RISC-V PMU
> identification and raw events matching between perf and the PMU. The
> HiFive Unmatched board can now use all the counters with named events.
>
What about PMU sampling support for U740 ? Do you have plans to support
them ?
> The work in these patches is completelly and directly dependent on
> the proposed SBI PMU patch [4], by Atish Patra.
>
> This series has been tested in the HiFive Unmatched board.
> OpenSBI[1] and U-Boot[2] patches are required to test it on the
> board, alongside with the series of patches that introduce RISC-V
> Perf support with the SBI PMU and sscofpmf extension [3-4]. The
> U-Boot fu740 dts [5] must be updated, may be fixed in future U-BOOT
> versions, with the events that will be tested, this comprehends
> changes to the riscv,raw-event-to-mhpmcounters entry. Also, an
> OpenSBI patch [6] proposes bitfield awareness for the DT raw-events,
> this will simplify, and improve, events description in the DT file.
>
> Here is the output of perf list and perf stat with all the available
> unmatched events monitoring a stress-ng trignometric stressor.
>
> HiFive Unmatched:
> =================
> perf list pmu
>
> instructions:
> atomic_memory_retired
> [Atomic memory operation retired]
> conditional_branch_retired
> [Conditional branch retired]
> exception_taken
> [Exception taken]
> fp_addition_retired
> [Floating-point addition retired]
> fp_div_sqrt_retired
> [Floating-point division or square-root retired]
> fp_fusedmadd_retired
> [Floating-point fused multiply-add retired]
> fp_load_retired
> [Floating-point load instruction retired]
> fp_multiplication_retired
> [Floating-point multiplication retired]
> fp_store_retired
> [Floating-point store instruction retired]
> integer_arithmetic_retired
> [Integer arithmetic instruction retired]
> integer_division_retired
> [Integer division instruction retired]
> integer_load_retired
> [Integer load instruction retired]
> integer_multiplication_retired
> [Integer multiplication instruction retired]
> integer_store_retired
> [Integer store instruction retired]
> jal_instruction_retired
> [JAL instruction retired]
> jalr_instruction_retired
> [JALR instruction retired]
> other_fp_retired
> [Other floating-point instruction retired]
> system_instruction_retired
> [System instruction retired]
>
> memory:
> data_tlb_miss
> [Data TLB miss]
> dcache_miss_mmio_accesses
> [Data cache miss or memory-mapped I/O access]
> dcache_writeback
> [Data cache write-back]
> icache_retired
> [Instruction cache miss]
> inst_tlb_miss
> [Instruction TLB miss]
> utlb_miss
> [UTLB miss]
>
> microarch:
> addressgen_interlock
> [Address-generation interlock]
> branch_direction_misprediction
> [Branch direction misprediction]
> branch_target_misprediction
> [Branch/jump target misprediction]
> csr_read_interlock
> [CSR read interlock]
> dcache_dtim_busy
> [Data cache/DTIM busy]
> fp_interlock
> [Floating-point interlock]
> icache_itim_busy
> [Instruction cache/ITIM busy]
> integer_multiplication_interlock
> [Integer multiplication interlock]
> longlat_interlock
> [Long-latency interlock]
> pipe_flush_csr_write
> [Pipeline flush from CSR write]
> pipe_flush_other_event
> [Pipeline flush from other event]
>
>
> perf stat
> -eexception_taken,integer_load_retired,integer_store_retired,atomic_memory_retired,system_instruction_retired,integer_arithmetic_retired,conditional_branch_retired,jal_instruction_retired,jalr_instruction_retired,integer_multiplication_retired,integer_division_retired,fp_load_retired,fp_store_retired,fp_addition_retired,fp_multiplication_retired,fp_fusedmadd_retired,fp_div_sqrt_retired,other_fp_retired,data_tlb_miss,dcache_miss_mmio_accesses,dcache_writeback,icache_retired,inst_tlb_miss,utlb_miss,addressgen_interlock,longlat_interlock,csr_read_interlock,icache_itim_busy,dcache_dtim_busy,branch_direction_misprediction,branch_target_misprediction,pipe_flush_csr_write,pipe_flush_other_event,integer_multiplication_interlock,fp_interlock
> stress-ng --cpu 1 --cpu-method trig -t 60s stress-ng: info: [500]
> setting to a 60 second run per stressor stress-ng: info: [500]
> dispatching hogs: 1 cpu stress-ng: info: [500] successful run
> completed in 60.02s (1 min, 0.02 secs)
>
> Performance counter stats for 'stress-ng --cpu 1 --cpu-method trig
> -t 60s':
>
> 233185 exception_taken
> (5.72%) 5010843878 integer_load_retired
> (5.73%) 4437123760
> integer_store_retired (5.73%)
> 875636 atomic_memory_retired
> (5.72%) 787401517 system_instruction_retired
> (5.73%) 58176497169
> integer_arithmetic_retired
> (5.74%) 9689155944 conditional_branch_retired
> (5.73%) 2141143732 jal_instruction_retired
> (5.72%) 624939326
> jalr_instruction_retired (5.72%)
> 1900272300 integer_multiplication_retired
> (5.72%) 29231344 integer_division_retired
> (5.72%) 1672274835 fp_load_retired
> (5.73%) 592215149
> fp_store_retired (5.73%)
> 13592616 fp_addition_retired
> (5.73%) 13597374 fp_multiplication_retired
> (5.72%) 1331957808 fp_fusedmadd_retired
> (5.72%) 592410829
> fp_div_sqrt_retired (5.72%)
> 227334317 other_fp_retired
> (5.72%) 95772283 data_tlb_miss
> (5.72%) 6291088 dcache_miss_mmio_accesses
> (5.72%) 55591 dcache_writeback
> (5.72%) 47394708
> icache_retired (5.72%)
> 62778259 inst_tlb_miss
> (5.72%) 10159938 utlb_miss
> (5.72%) 424446212 addressgen_interlock
> (5.72%) 849061809
> longlat_interlock (5.72%)
> 0 csr_read_interlock
> (5.71%) 16924613138 icache_itim_busy
> (5.71%) 204163844 dcache_dtim_busy
> (5.70%) 175163620
> branch_direction_misprediction
> (5.72%) 202874026 branch_target_misprediction
> (5.71%) 433228932 pipe_flush_csr_write
> (5.71%) 0 pipe_flush_other_event
> (5.71%) 429384915
> integer_multiplication_interlock
> (5.71%) 8635530214 fp_interlock
> (5.71%)
>
> 60.044837787 seconds time elapsed
>
> 60.001431000 seconds user
> 0.033660000 seconds sys
>
>
> [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
> [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
> [4]
> http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> [5]
> https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
> [6]
> https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
>
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
>
> This work was developed at INESC-ID, Instituto Superior Técnico,
> Universidade de Lisboa.
>
> João Mário Domingos (4):
> RISC-V: Create unique identification for SoC PMU
> RISC-V: Support CPUID for risc-v in perf
> RISC-V: Added generic pmu-events mapfile
> RISC-V: Added HiFive Unmatched PMU events
>
> arch/riscv/kernel/sbi.c | 3 +
> drivers/perf/riscv_pmu.c | 18 ++++
> drivers/perf/riscv_pmu_sbi.c | 46 ++++++++++
> tools/perf/arch/riscv/util/Build | 1 +
> tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
> .../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
> .../arch/riscv/sifive/u74/instructions.json | 92
> +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json |
> 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57
> ++++++++++++ 10 files changed, 350 insertions(+)
> create mode 100644 tools/perf/arch/riscv/util/header.c
> create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> create mode 100644
> tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> create mode 100644
> tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/4] RISC-V: Create unique identification for SoC PMU
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
@ 2021-11-15 8:23 ` Nikita Shubin
2021-11-16 15:54 ` João Mário Domingos
0 siblings, 1 reply; 23+ messages in thread
From: Nikita Shubin @ 2021-11-15 8:23 UTC (permalink / raw)
To: João Mário Domingos
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
Hello Mário.
On Tue, 9 Nov 2021 10:25:52 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> The SBI PMU platform driver did not provide any identification for
> perf events matching. This patch introduces a new sysfs file inside
> the platform device (soc:pmu/id) for pmu identification.
>
> The identification is a 64-bit value generated as:
> [63-32]: mvendorid;
> [31]: marchid[MSB];
> [30-16]: marchid[15-0];
> [15-0]: mimpid[15MSBs];
>
> The CSRs are detailed in the RISC-V privileged spec [1].
> The marchid is split in MSB + 15LSBs, due to the MSB being used for
> open-source architecture identification.
>
This patch doesn't compile and also has a warning:
```
drivers/perf/riscv_pmu_sbi.c:239:43: error: 'pmu_sbi_id_show'
undeclared here (not in a function)
239 | static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
| ^~~~~~~~~~~~~~~
include/linux/sysfs.h:104:19: note: in definition of macro '__ATTR'
104 | .show = _show,
\
| ^~~~~
drivers/perf/riscv_pmu_sbi.c:239:8: note: in expansion of macro
'DEVICE_ATTR'
239 | static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
| ^~~~~~~~~~~
drivers/perf/riscv_pmu_sbi.c: In function 'pmu_sbi_id_show':
drivers/perf/riscv_pmu_sbi.c:675:29: warning: format '%lx' expects
argument of type 'long unsigned int',
but argument 3 has type 'uint64_t' {aka 'long long unsigned int'}
[-Wformat=]
675 | len = sprintf(buf, "0x%lx\n", pmu_sbi_get_pmu_id());
| ~~^ ~~~~~~~~~~~~~~~~~~~~
| | |
| | uint64_t {aka long long
unsigned int}
| long unsigned int
| %llx
```
May be you wanted to place DEVICE_ATTR after pmu_sbi_id_show function
declaration ?
Please check with a clean build.
Yours,
Nikita Shubin
> [1] https://github.com/riscv/riscv-isa-manual
>
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> ---
> arch/riscv/kernel/sbi.c | 3 +++
> drivers/perf/riscv_pmu_sbi.c | 46
> ++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+)
>
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 7402a417f38e..4e4f5671b864 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -551,16 +551,19 @@ long sbi_get_mvendorid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> }
> +EXPORT_SYMBOL(sbi_get_mvendorid);
>
> long sbi_get_marchid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> }
> +EXPORT_SYMBOL(sbi_get_marchid);
>
> long sbi_get_mimpid(void)
> {
> return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> }
> +EXPORT_SYMBOL(sbi_get_mimpid);
>
> static void sbi_send_cpumask_ipi(const struct cpumask *target)
> {
> diff --git a/drivers/perf/riscv_pmu_sbi.c
> b/drivers/perf/riscv_pmu_sbi.c index 7a68dfa89f6f..f913d8ddfe73 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -236,6 +236,15 @@ static const struct pmu_event_data
> pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX] },
> };
>
> +static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
> +
> +static struct attribute *pmu_sbi_attrs[] = {
> + &dev_attr_id.attr,
> + NULL
> +};
> +
> +ATTRIBUTE_GROUPS(pmu_sbi);
> +
> static int pmu_sbi_ctr_get_width(int idx)
> {
> return pmu_ctr_list[idx].width;
> @@ -642,6 +651,36 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu
> *pmu, struct platform_device *pde return 0;
> }
>
> +static uint64_t pmu_sbi_get_pmu_id(void)
> +{
> + union sbi_pmu_id {
> + uint64_t value;
> + struct {
> + uint16_t imp:16;
> + uint16_t arch:16;
> + uint32_t vendor:32;
> + };
> + }pmuid;
> +
> + pmuid.value = 0;
> + pmuid.vendor = (uint32_t) sbi_get_mvendorid();
> + pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) |
> ( sbi_get_marchid() & 0x7FFF );
> + pmuid.imp = (sbi_get_mimpid() >> 16);
> +
> + return pmuid.value;
> +}
> +
> +static ssize_t pmu_sbi_id_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + int len;
> + len = sprintf(buf, "0x%lx\n", pmu_sbi_get_pmu_id());
> + if (len <= 0)
> + dev_err(dev, "mydrv: Invalid sprintf len: %dn", len);
> +
> + return len;
> +}
> +
> static int pmu_sbi_device_probe(struct platform_device *pdev)
> {
> struct riscv_pmu *pmu = NULL;
> @@ -680,6 +719,13 @@ static int pmu_sbi_device_probe(struct
> platform_device *pdev) pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
> pmu->ctr_read = pmu_sbi_ctr_read;
>
> + ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group);
> + if (ret) {
> + dev_err(&pdev->dev, "sysfs creation failed\n");
> + return ret;
> + }
> + pdev->dev.groups = pmu_sbi_groups;
> +
> ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING,
> &pmu->node); if (ret)
> return ret;
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
` (4 preceding siblings ...)
2021-11-10 13:55 ` [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
@ 2021-11-16 15:48 ` João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
` (4 more replies)
5 siblings, 5 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:48 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: atish.patra, anup.patel, linux-riscv, nikita.shubin, joao.mario
This series of patches introduces support for the RISC-V PMU identification and raw events matching between perf and the PMU.
The HiFive Unmatched board can now use all the counters with named events.
The work in these patches is completelly and directly dependent on the proposed SBI PMU patch [4], by Atish Patra.
This series has been tested in the HiFive Unmatched board.
OpenSBI[1] and U-Boot[2] patches are required to test it on the board, alongside with the series of patches that introduce RISC-V Perf support with the SBI PMU and sscofpmf extension [3-4].
The U-Boot fu740 dts [5] must be updated, may be fixed in future U-BOOT versions, with the events that will be tested, this comprehends changes to the riscv,raw-event-to-mhpmcounters entry. Also, an OpenSBI patch [6] proposes bitfield awareness for the DT raw-events, this will simplify, and improve, events description in the DT file.
Here is the output of perf list and perf stat with all the available unmatched events monitoring a stress-ng trignometric stressor.
HiFive Unmatched:
=================
perf list pmu
instructions:
atomic_memory_retired
[Atomic memory operation retired]
conditional_branch_retired
[Conditional branch retired]
exception_taken
[Exception taken]
fp_addition_retired
[Floating-point addition retired]
fp_div_sqrt_retired
[Floating-point division or square-root retired]
fp_fusedmadd_retired
[Floating-point fused multiply-add retired]
fp_load_retired
[Floating-point load instruction retired]
fp_multiplication_retired
[Floating-point multiplication retired]
fp_store_retired
[Floating-point store instruction retired]
integer_arithmetic_retired
[Integer arithmetic instruction retired]
integer_division_retired
[Integer division instruction retired]
integer_load_retired
[Integer load instruction retired]
integer_multiplication_retired
[Integer multiplication instruction retired]
integer_store_retired
[Integer store instruction retired]
jal_instruction_retired
[JAL instruction retired]
jalr_instruction_retired
[JALR instruction retired]
other_fp_retired
[Other floating-point instruction retired]
system_instruction_retired
[System instruction retired]
memory:
data_tlb_miss
[Data TLB miss]
dcache_miss_mmio_accesses
[Data cache miss or memory-mapped I/O access]
dcache_writeback
[Data cache write-back]
icache_retired
[Instruction cache miss]
inst_tlb_miss
[Instruction TLB miss]
utlb_miss
[UTLB miss]
microarch:
addressgen_interlock
[Address-generation interlock]
branch_direction_misprediction
[Branch direction misprediction]
branch_target_misprediction
[Branch/jump target misprediction]
csr_read_interlock
[CSR read interlock]
dcache_dtim_busy
[Data cache/DTIM busy]
fp_interlock
[Floating-point interlock]
icache_itim_busy
[Instruction cache/ITIM busy]
integer_multiplication_interlock
[Integer multiplication interlock]
longlat_interlock
[Long-latency interlock]
pipe_flush_csr_write
[Pipeline flush from CSR write]
pipe_flush_other_event
[Pipeline flush from other event]
perf stat -eexception_taken,integer_load_retired,integer_store_retired,atomic_memory_retired,system_instruction_retired,integer_arithmetic_retired,conditional_branch_retired,jal_instruction_retired,jalr_instruction_retired,integer_multiplication_retired,integer_division_retired,fp_load_retired,fp_store_retired,fp_addition_retired,fp_multiplication_retired,fp_fusedmadd_retired,fp_div_sqrt_retired,other_fp_retired,data_tlb_miss,dcache_miss_mmio_accesses,dcache_writeback,icache_retired,inst_tlb_miss,utlb_miss,addressgen_interlock,longlat_interlock,csr_read_interlock,icache_itim_busy,dcache_dtim_busy,branch_direction_misprediction,branch_target_misprediction,pipe_flush_csr_write,pipe_flush_other_event,integer_multiplication_interlock,fp_interlock stress-ng --cpu 1 --cpu-method trig -t 60s
stress-ng: info: [500] setting to a 60 second run per stressor
stress-ng: info: [500] dispatching hogs: 1 cpu
stress-ng: info: [500] successful run completed in 60.02s (1 min, 0.02 secs)
Performance counter stats for 'stress-ng --cpu 1 --cpu-method trig -t 60s':
233185 exception_taken (5.72%)
5010843878 integer_load_retired (5.73%)
4437123760 integer_store_retired (5.73%)
875636 atomic_memory_retired (5.72%)
787401517 system_instruction_retired (5.73%)
58176497169 integer_arithmetic_retired (5.74%)
9689155944 conditional_branch_retired (5.73%)
2141143732 jal_instruction_retired (5.72%)
624939326 jalr_instruction_retired (5.72%)
1900272300 integer_multiplication_retired (5.72%)
29231344 integer_division_retired (5.72%)
1672274835 fp_load_retired (5.73%)
592215149 fp_store_retired (5.73%)
13592616 fp_addition_retired (5.73%)
13597374 fp_multiplication_retired (5.72%)
1331957808 fp_fusedmadd_retired (5.72%)
592410829 fp_div_sqrt_retired (5.72%)
227334317 other_fp_retired (5.72%)
95772283 data_tlb_miss (5.72%)
6291088 dcache_miss_mmio_accesses (5.72%)
55591 dcache_writeback (5.72%)
47394708 icache_retired (5.72%)
62778259 inst_tlb_miss (5.72%)
10159938 utlb_miss (5.72%)
424446212 addressgen_interlock (5.72%)
849061809 longlat_interlock (5.72%)
0 csr_read_interlock (5.71%)
16924613138 icache_itim_busy (5.71%)
204163844 dcache_dtim_busy (5.70%)
175163620 branch_direction_misprediction (5.72%)
202874026 branch_target_misprediction (5.71%)
433228932 pipe_flush_csr_write (5.71%)
0 pipe_flush_other_event (5.71%)
429384915 integer_multiplication_interlock (5.71%)
8635530214 fp_interlock (5.71%)
60.044837787 seconds time elapsed
60.001431000 seconds user
0.033660000 seconds sys
[1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
[2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
[3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
[4] http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
[5] https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
[6] https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
This work was developed at INESC-ID, Instituto Superior Técnico, Universidade de Lisboa.
---
Changes in v2:
- Fix compilation errors and warnings
- Remove space idents
- Correct formatting
João Mário Domingos (4):
RISC-V: Create unique identification for SoC PMU
RISC-V: Support CPUID for risc-v in perf
RISC-V: Added generic pmu-events mapfile
RISC-V: Added HiFive Unmatched PMU events
arch/riscv/kernel/sbi.c | 3 +
drivers/perf/riscv_pmu.c | 18 ++++
drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++
tools/perf/arch/riscv/util/Build | 1 +
tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
.../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
.../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++
10 files changed, 351 insertions(+)
create mode 100644 tools/perf/arch/riscv/util/header.c
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
@ 2021-11-16 15:48 ` João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
` (3 subsequent siblings)
4 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:48 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: atish.patra, anup.patel, linux-riscv, nikita.shubin, joao.mario
The SBI PMU platform driver did not provide any identification for
perf events matching. This patch introduces a new sysfs file inside the
platform device (soc:pmu/id) for pmu identification.
The identification is a 64-bit value generated as:
[63-32]: mvendorid;
[31]: marchid[MSB];
[30-16]: marchid[15-0];
[15-0]: mimpid[15MSBs];
The CSRs are detailed in the RISC-V privileged spec [1].
The marchid is split in MSB + 15LSBs, due to the MSB being used for
open-source architecture identification.
[1] https://github.com/riscv/riscv-isa-manual
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
arch/riscv/kernel/sbi.c | 3 +++
drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 7402a417f38e..4e4f5671b864 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -551,16 +551,19 @@ long sbi_get_mvendorid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
}
+EXPORT_SYMBOL(sbi_get_mvendorid);
long sbi_get_marchid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
}
+EXPORT_SYMBOL(sbi_get_marchid);
long sbi_get_mimpid(void)
{
return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
}
+EXPORT_SYMBOL(sbi_get_mimpid);
static void sbi_send_cpumask_ipi(const struct cpumask *target)
{
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 7a68dfa89f6f..a69251ec7a3e 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -642,6 +642,46 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
return 0;
}
+static uint64_t pmu_sbi_get_pmu_id(void)
+{
+ union sbi_pmu_id {
+ uint64_t value;
+ struct {
+ uint16_t imp:16;
+ uint16_t arch:16;
+ uint32_t vendor:32;
+ };
+ } pmuid;
+
+ pmuid.value = 0;
+ pmuid.vendor = (uint32_t) sbi_get_mvendorid();
+ pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) | (sbi_get_marchid() & 0x7FFF);
+ pmuid.imp = (sbi_get_mimpid() >> 16);
+
+ return pmuid.value;
+}
+
+static ssize_t pmu_sbi_id_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len;
+
+ len = sprintf(buf, "0x%llx\n", pmu_sbi_get_pmu_id());
+ if (len <= 0)
+ dev_err(dev, "mydrv: Invalid sprintf len: %dn", len);
+
+ return len;
+}
+
+static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
+
+static struct attribute *pmu_sbi_attrs[] = {
+ &dev_attr_id.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(pmu_sbi);
+
static int pmu_sbi_device_probe(struct platform_device *pdev)
{
struct riscv_pmu *pmu = NULL;
@@ -680,6 +720,13 @@ static int pmu_sbi_device_probe(struct platform_device *pdev)
pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
pmu->ctr_read = pmu_sbi_ctr_read;
+ ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group);
+ if (ret) {
+ dev_err(&pdev->dev, "sysfs creation failed\n");
+ return ret;
+ }
+ pdev->dev.groups = pmu_sbi_groups;
+
ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
if (ret)
return ret;
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
@ 2021-11-16 15:48 ` João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
` (2 subsequent siblings)
4 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:48 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: atish.patra, anup.patel, linux-riscv, nikita.shubin, joao.mario
This patch creates the header.c file for the risc-v architecture and introduces support for
PMU identification through sysfs.
It is now possible to configure pmu-events in risc-v.
Depends on patch [1], that introduces the id sysfs file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
drivers/perf/riscv_pmu.c | 18 ++++++++
tools/perf/arch/riscv/util/Build | 1 +
| 66 +++++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
create mode 100644 tools/perf/arch/riscv/util/header.c
diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index 0c853e23f679..3752ffd4edaf 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -17,6 +17,23 @@
#include <asm/sbi.h>
+PMU_FORMAT_ATTR(event, "config:0-63");
+
+static struct attribute *riscv_arch_formats_attr[] = {
+ &format_attr_event.attr,
+ NULL,
+};
+
+static struct attribute_group riscv_pmu_format_group = {
+ .name = "format",
+ .attrs = riscv_arch_formats_attr,
+};
+
+static const struct attribute_group *riscv_pmu_attr_groups[] = {
+ &riscv_pmu_format_group,
+ NULL,
+};
+
static unsigned long csr_read_num(int csr_num)
{
#define switchcase_csr_read(__csr_num, __val) {\
@@ -314,6 +331,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
cpuc->events[i] = NULL;
}
pmu->pmu = (struct pmu) {
+ .attr_groups = riscv_pmu_attr_groups,
.event_init = riscv_pmu_event_init,
.add = riscv_pmu_add,
.del = riscv_pmu_del,
diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
index 7d3050134ae0..603dbb5ae4dc 100644
--- a/tools/perf/arch/riscv/util/Build
+++ b/tools/perf/arch/riscv/util/Build
@@ -1,4 +1,5 @@
perf-y += perf_regs.o
+perf-y += header.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
--git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c
new file mode 100644
index 000000000000..b4ca8a768f11
--- /dev/null
+++ b/tools/perf/arch/riscv/util/header.c
@@ -0,0 +1,66 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <api/fs/fs.h>
+#include <errno.h>
+#include "../../util/debug.h"
+#include "../../util/header.h"
+
+#define STR_LEN 1024
+#define ID_SIZE 64
+
+static int _get_cpuid(char *buf, size_t sz)
+{
+ const char *sysfs = sysfs__mountpoint();
+ u64 id = 0;
+ char path[PATH_MAX];
+ FILE *file;
+
+ if (!sysfs || sz < ID_SIZE)
+ return -EINVAL;
+
+ scnprintf(path, PATH_MAX, "%s/devices/platform/soc/soc:pmu/id",
+ sysfs);
+
+ file = fopen(path, "r");
+ if (!file) {
+ pr_debug("fopen failed for file %s\n", path);
+ return -EINVAL;
+ }
+ if (!fgets(buf, ID_SIZE, file)) {
+ fclose(file);
+ return -EINVAL;
+ }
+
+ fclose(file);
+
+ /*Check if value is numeric and remove special characters*/
+ id = strtoul(buf, NULL, 16);
+ if (!id)
+ return -EINVAL;
+ scnprintf(buf, ID_SIZE, "0x%lx", id);
+
+ return 0;
+}
+
+char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
+{
+ char *buf = NULL;
+ int res;
+
+ if (!pmu)
+ return NULL;
+
+ buf = malloc(ID_SIZE);
+ if (!buf)
+ return NULL;
+
+ /* read id */
+ res = _get_cpuid(buf, ID_SIZE);
+ if (res) {
+ pr_err("failed to get cpuid string for PMU %s\n", pmu->name);
+ free(buf);
+ buf = NULL;
+ }
+
+ return buf;
+}
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
@ 2021-11-16 15:48 ` João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-17 12:25 ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
4 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:48 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: atish.patra, anup.patel, linux-riscv, nikita.shubin, joao.mario
The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 14 +++++++++++++
.../pmu-events/arch/riscv/riscv-generic.json | 20 +++++++++++++++++++
2 files changed, 34 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
new file mode 100644
index 000000000000..4f2aa199d9cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+# MIDR,Version,JSON/file/pathname,Type
+#
+# where
+# MIDR Processor version
+# Variant[23:20] and Revision [3:0] should be zero.
+# Version could be used to track version of JSON file
+# but currently unused.
+# JSON/file/pathname is the path to JSON file, relative
+# to tools/perf/pmu-events/arch/riscv/.
+# Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
new file mode 100644
index 000000000000..013e50efad99
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
@@ -0,0 +1,20 @@
+[
+ {
+ "PublicDescription": "CPU Cycles",
+ "EventCode": "0x00",
+ "EventName": "riscv_cycles",
+ "BriefDescription": "CPU cycles RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Time",
+ "EventCode": "0x01",
+ "EventName": "riscv_time",
+ "BriefDescription": "CPU time RISC-V generic counter"
+ },
+ {
+ "PublicDescription": "CPU Instructions",
+ "EventCode": "0x02",
+ "EventName": "riscv_instret",
+ "BriefDescription": "CPU retired instructions RISC-V generic counter"
+ }
+]
\ No newline at end of file
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
` (2 preceding siblings ...)
2021-11-16 15:48 ` [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
@ 2021-11-16 15:48 ` João Mário Domingos
2021-11-17 11:25 ` Nikita Shubin
2021-11-17 12:25 ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
4 siblings, 1 reply; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:48 UTC (permalink / raw)
To: palmer, paul.walmsley, aou
Cc: atish.patra, anup.patel, linux-riscv, nikita.shubin, joao.mario
This patch contains all the available events for the HiFive Unmatched performance monitoring unit.
Depends on patch [3], for the base mapfile.csv file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++
4 files changed, 182 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 4f2aa199d9cb..bda3fb9382f1 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -12,3 +12,4 @@
#
#
#Family-model,Version,Filename,EventType
+0x48980072018,v1,sifive/u74,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
new file mode 100644
index 000000000000..5eab718c9256
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
@@ -0,0 +1,92 @@
+[
+ {
+ "EventName": "EXCEPTION_TAKEN",
+ "EventCode": "0x0000100",
+ "BriefDescription": "Exception taken"
+ },
+ {
+ "EventName": "INTEGER_LOAD_RETIRED",
+ "EventCode": "0x0000200",
+ "BriefDescription": "Integer load instruction retired"
+ },
+ {
+ "EventName": "INTEGER_STORE_RETIRED",
+ "EventCode": "0x0000400",
+ "BriefDescription": "Integer store instruction retired"
+ },
+ {
+ "EventName": "ATOMIC_MEMORY_RETIRED",
+ "EventCode": "0x0000800",
+ "BriefDescription": "Atomic memory operation retired"
+ },
+ {
+ "EventName": "SYSTEM_INSTRUCTION_RETIRED",
+ "EventCode": "0x0001000",
+ "BriefDescription": "System instruction retired"
+ },
+ {
+ "EventName": "INTEGER_ARITHMETIC_RETIRED",
+ "EventCode": "0x0002000",
+ "BriefDescription": "Integer arithmetic instruction retired"
+ },
+ {
+ "EventName": "CONDITIONAL_BRANCH_RETIRED",
+ "EventCode": "0x0004000",
+ "BriefDescription": "Conditional branch retired"
+ },
+ {
+ "EventName": "JAL_INSTRUCTION_RETIRED",
+ "EventCode": "0x0008000",
+ "BriefDescription": "JAL instruction retired"
+ },
+ {
+ "EventName": "JALR_INSTRUCTION_RETIRED",
+ "EventCode": "0x0010000",
+ "BriefDescription": "JALR instruction retired"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0020000",
+ "BriefDescription": "Integer multiplication instruction retired"
+ },
+ {
+ "EventName": "INTEGER_DIVISION_RETIRED",
+ "EventCode": "0x0040000",
+ "BriefDescription": "Integer division instruction retired"
+ },
+ {
+ "EventName": "FP_LOAD_RETIRED",
+ "EventCode": "0x0080000",
+ "BriefDescription": "Floating-point load instruction retired"
+ },
+ {
+ "EventName": "FP_STORE_RETIRED",
+ "EventCode": "0x0100000",
+ "BriefDescription": "Floating-point store instruction retired"
+ },
+ {
+ "EventName": "FP_ADDITION_RETIRED",
+ "EventCode": "0x0200000",
+ "BriefDescription": "Floating-point addition retired"
+ },
+ {
+ "EventName": "FP_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0400000",
+ "BriefDescription": "Floating-point multiplication retired"
+ },
+ {
+ "EventName": "FP_FUSEDMADD_RETIRED",
+ "EventCode": "0x0800000",
+ "BriefDescription": "Floating-point fused multiply-add retired"
+ },
+ {
+ "EventName": "FP_DIV_SQRT_RETIRED",
+ "EventCode": "0x1000000",
+ "BriefDescription": "Floating-point division or square-root retired"
+ },
+ {
+ "EventName": "OTHER_FP_RETIRED",
+ "EventCode": "0x2000000",
+ "BriefDescription": "Other floating-point instruction retired"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
new file mode 100644
index 000000000000..be1a46312ac3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
@@ -0,0 +1,32 @@
+[
+ {
+ "EventName": "ICACHE_RETIRED",
+ "EventCode": "0x0000102",
+ "BriefDescription": "Instruction cache miss"
+ },
+ {
+ "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+ "EventCode": "0x0000202",
+ "BriefDescription": "Data cache miss or memory-mapped I/O access"
+ },
+ {
+ "EventName": "DCACHE_WRITEBACK",
+ "EventCode": "0x0000402",
+ "BriefDescription": "Data cache write-back"
+ },
+ {
+ "EventName": "INST_TLB_MISS",
+ "EventCode": "0x0000802",
+ "BriefDescription": "Instruction TLB miss"
+ },
+ {
+ "EventName": "DATA_TLB_MISS",
+ "EventCode": "0x0001002",
+ "BriefDescription": "Data TLB miss"
+ },
+ {
+ "EventName": "UTLB_MISS",
+ "EventCode": "0x0002002",
+ "BriefDescription": "UTLB miss"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
new file mode 100644
index 000000000000..50ffa55418cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x0000101",
+ "BriefDescription": "Address-generation interlock"
+ },
+ {
+ "EventName": "LONGLAT_INTERLOCK",
+ "EventCode": "0x0000201",
+ "BriefDescription": "Long-latency interlock"
+ },
+ {
+ "EventName": "CSR_READ_INTERLOCK",
+ "EventCode": "0x0000401",
+ "BriefDescription": "CSR read interlock"
+ },
+ {
+ "EventName": "ICACHE_ITIM_BUSY",
+ "EventCode": "0x0000801",
+ "BriefDescription": "Instruction cache/ITIM busy"
+ },
+ {
+ "EventName": "DCACHE_DTIM_BUSY",
+ "EventCode": "0x0001001",
+ "BriefDescription": "Data cache/DTIM busy"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x0002001",
+ "BriefDescription": "Branch direction misprediction"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x0004001",
+ "BriefDescription": "Branch/jump target misprediction"
+ },
+ {
+ "EventName": "PIPE_FLUSH_CSR_WRITE",
+ "EventCode": "0x0008001",
+ "BriefDescription": "Pipeline flush from CSR write"
+ },
+ {
+ "EventName": "PIPE_FLUSH_OTHER_EVENT",
+ "EventCode": "0x0010001",
+ "BriefDescription": "Pipeline flush from other event"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+ "EventCode": "0x0020001",
+ "BriefDescription": "Integer multiplication interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x0040001",
+ "BriefDescription": "Floating-point interlock"
+ }
+]
\ No newline at end of file
--
2.17.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/4] RISC-V: Create unique identification for SoC PMU
2021-11-15 8:23 ` Nikita Shubin
@ 2021-11-16 15:54 ` João Mário Domingos
0 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-16 15:54 UTC (permalink / raw)
To: Nikita Shubin
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
On Mon, Nov 15, 2021 at 11:23:16AM +0300, Nikita Shubin wrote:
> Hello Mário.
>
> On Tue, 9 Nov 2021 10:25:52 +0000
> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
>
> > The SBI PMU platform driver did not provide any identification for
> > perf events matching. This patch introduces a new sysfs file inside
> > the platform device (soc:pmu/id) for pmu identification.
> >
> > The identification is a 64-bit value generated as:
> > [63-32]: mvendorid;
> > [31]: marchid[MSB];
> > [30-16]: marchid[15-0];
> > [15-0]: mimpid[15MSBs];
> >
> > The CSRs are detailed in the RISC-V privileged spec [1].
> > The marchid is split in MSB + 15LSBs, due to the MSB being used for
> > open-source architecture identification.
> >
>
> This patch doesn't compile and also has a warning:
Corrected in v2.
> ```
> drivers/perf/riscv_pmu_sbi.c:239:43: error: 'pmu_sbi_id_show'
> undeclared here (not in a function)
> 239 | static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
> | ^~~~~~~~~~~~~~~
> include/linux/sysfs.h:104:19: note: in definition of macro '__ATTR'
> 104 | .show = _show,
> \
> | ^~~~~
> drivers/perf/riscv_pmu_sbi.c:239:8: note: in expansion of macro
> 'DEVICE_ATTR'
> 239 | static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
> | ^~~~~~~~~~~
> drivers/perf/riscv_pmu_sbi.c: In function 'pmu_sbi_id_show':
> drivers/perf/riscv_pmu_sbi.c:675:29: warning: format '%lx' expects
> argument of type 'long unsigned int',
> but argument 3 has type 'uint64_t' {aka 'long long unsigned int'}
> [-Wformat=]
> 675 | len = sprintf(buf, "0x%lx\n", pmu_sbi_get_pmu_id());
> | ~~^ ~~~~~~~~~~~~~~~~~~~~
> | | |
> | | uint64_t {aka long long
> unsigned int}
> | long unsigned int
> | %llx
> ```
>
> May be you wanted to place DEVICE_ATTR after pmu_sbi_id_show function
> declaration ?
>
> Please check with a clean build.
Recompiled everything with a clean build and the necessary changes are
reflected in version 2 of the series.
If you have the time, please check again.
>
> Yours,
> Nikita Shubin
>
> > [1] https://github.com/riscv/riscv-isa-manual
> >
> > Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> > ---
> > arch/riscv/kernel/sbi.c | 3 +++
> > drivers/perf/riscv_pmu_sbi.c | 46
> > ++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> > index 7402a417f38e..4e4f5671b864 100644
> > --- a/arch/riscv/kernel/sbi.c
> > +++ b/arch/riscv/kernel/sbi.c
> > @@ -551,16 +551,19 @@ long sbi_get_mvendorid(void)
> > {
> > return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> > }
> > +EXPORT_SYMBOL(sbi_get_mvendorid);
> >
> > long sbi_get_marchid(void)
> > {
> > return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> > }
> > +EXPORT_SYMBOL(sbi_get_marchid);
> >
> > long sbi_get_mimpid(void)
> > {
> > return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> > }
> > +EXPORT_SYMBOL(sbi_get_mimpid);
> >
> > static void sbi_send_cpumask_ipi(const struct cpumask *target)
> > {
> > diff --git a/drivers/perf/riscv_pmu_sbi.c
> > b/drivers/perf/riscv_pmu_sbi.c index 7a68dfa89f6f..f913d8ddfe73 100644
> > --- a/drivers/perf/riscv_pmu_sbi.c
> > +++ b/drivers/perf/riscv_pmu_sbi.c
> > @@ -236,6 +236,15 @@ static const struct pmu_event_data
> > pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX] },
> > };
> >
> > +static DEVICE_ATTR(id, S_IRUGO | S_IWUSR, pmu_sbi_id_show, 0);
> > +
> > +static struct attribute *pmu_sbi_attrs[] = {
> > + &dev_attr_id.attr,
> > + NULL
> > +};
> > +
> > +ATTRIBUTE_GROUPS(pmu_sbi);
> > +
> > static int pmu_sbi_ctr_get_width(int idx)
> > {
> > return pmu_ctr_list[idx].width;
> > @@ -642,6 +651,36 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu
> > *pmu, struct platform_device *pde return 0;
> > }
> >
> > +static uint64_t pmu_sbi_get_pmu_id(void)
> > +{
> > + union sbi_pmu_id {
> > + uint64_t value;
> > + struct {
> > + uint16_t imp:16;
> > + uint16_t arch:16;
> > + uint32_t vendor:32;
> > + };
> > + }pmuid;
> > +
> > + pmuid.value = 0;
> > + pmuid.vendor = (uint32_t) sbi_get_mvendorid();
> > + pmuid.arch = (sbi_get_marchid() >> (63 - 15) & (1 << 15)) |
> > ( sbi_get_marchid() & 0x7FFF );
> > + pmuid.imp = (sbi_get_mimpid() >> 16);
> > +
> > + return pmuid.value;
> > +}
> > +
> > +static ssize_t pmu_sbi_id_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + int len;
> > + len = sprintf(buf, "0x%lx\n", pmu_sbi_get_pmu_id());
> > + if (len <= 0)
> > + dev_err(dev, "mydrv: Invalid sprintf len: %dn", len);
> > +
> > + return len;
> > +}
> > +
> > static int pmu_sbi_device_probe(struct platform_device *pdev)
> > {
> > struct riscv_pmu *pmu = NULL;
> > @@ -680,6 +719,13 @@ static int pmu_sbi_device_probe(struct
> > platform_device *pdev) pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
> > pmu->ctr_read = pmu_sbi_ctr_read;
> >
> > + ret = sysfs_create_group(&pdev->dev.kobj, &pmu_sbi_group);
> > + if (ret) {
> > + dev_err(&pdev->dev, "sysfs creation failed\n");
> > + return ret;
> > + }
> > + pdev->dev.groups = pmu_sbi_groups;
> > +
> > ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING,
> > &pmu->node); if (ret)
> > return ret;
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events
2021-11-16 15:48 ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
@ 2021-11-17 11:25 ` Nikita Shubin
2021-11-22 15:24 ` João Mário Domingos
0 siblings, 1 reply; 23+ messages in thread
From: Nikita Shubin @ 2021-11-17 11:25 UTC (permalink / raw)
To: João Mário Domingos
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
On Tue, 16 Nov 2021 15:48:12 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
Hello Mario!
> + {
> + "EventName": "UTLB_MISS",
> + "EventCode": "0x0002002",
> + "BriefDescription": "UTLB miss"
> + }
I don't see such thing in FU740 v1p3 manual - am i missing something ?
Yours,
Nikita Shubin
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
` (3 preceding siblings ...)
2021-11-16 15:48 ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
@ 2021-11-17 12:25 ` Nikita Shubin
2021-11-18 8:00 ` Atish Patra
4 siblings, 1 reply; 23+ messages in thread
From: Nikita Shubin @ 2021-11-17 12:25 UTC (permalink / raw)
To: João Mário Domingos
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
On Tue, 16 Nov 2021 15:48:08 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
Hello Mario!
Thank you for your patch series.
I have reproduced your test with some u-boot dts tinkering, and got
similar results.
However,
>
> [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
OpenSBI sscofpmf has been merged.
> [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> [5]
> https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
Is missing the adaptation for OpenSBI bitmap patch for
"raw-event-to-mhpmcounters".
> [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
The link is broken.
> [4]
> http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> [6]
> https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
>
There is a version 2 submitted, and it won't apply as require rebasing
and some renaming.
Please share your u-boot dts changes - they should be small and provide
a common base for this series.
Tested-by: Nikita Shubin <n.shubin@yadro.com>
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
>
> This work was developed at INESC-ID, Instituto Superior Técnico,
> Universidade de Lisboa.
>
> ---
> Changes in v2:
> - Fix compilation errors and warnings
> - Remove space idents
> - Correct formatting
>
> João Mário Domingos (4):
> RISC-V: Create unique identification for SoC PMU
> RISC-V: Support CPUID for risc-v in perf
> RISC-V: Added generic pmu-events mapfile
> RISC-V: Added HiFive Unmatched PMU events
>
> arch/riscv/kernel/sbi.c | 3 +
> drivers/perf/riscv_pmu.c | 18 ++++
> drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++
> tools/perf/arch/riscv/util/Build | 1 +
> tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
> .../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
> .../arch/riscv/sifive/u74/instructions.json | 92
> +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json |
> 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57
> ++++++++++++ 10 files changed, 351 insertions(+)
> create mode 100644 tools/perf/arch/riscv/util/header.c
> create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> create mode 100644
> tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> create mode 100644
> tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-17 12:25 ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
@ 2021-11-18 8:00 ` Atish Patra
2021-11-22 14:57 ` João Mário Domingos
0 siblings, 1 reply; 23+ messages in thread
From: Atish Patra @ 2021-11-18 8:00 UTC (permalink / raw)
To: Nikita Shubin
Cc: João Mário Domingos, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Atish Patra, Anup Patel, linux-riscv
On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
>
> On Tue, 16 Nov 2021 15:48:08 +0000
> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
>
> Hello Mario!
>
> Thank you for your patch series.
>
> I have reproduced your test with some u-boot dts tinkering, and got
> similar results.
>
> However,
>
> >
> > [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
>
> OpenSBI sscofpmf has been merged.
>
> > [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> > [5]
> > https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
>
> Is missing the adaptation for OpenSBI bitmap patch for
> "raw-event-to-mhpmcounters".
My patch was just an example and predates before the bitmap patch
posted by Vincent.
I will update the U-boot patch along with the next kernel version.
>
> > [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
>
> The link is broken.
>
Sorry. This should be
https://github.com/atishp04/linux/tree/sbi_pmu_v4
> > [4]
> > http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
>
> > [6]
> > https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
> >
>
> There is a version 2 submitted, and it won't apply as require rebasing
> and some renaming.
>
> Please share your u-boot dts changes - they should be small and provide
> a common base for this series.
>
Yes. That would be really helpful to have a DT path with all the
entries for easier testing.
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
>
> > Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> >
> > This work was developed at INESC-ID, Instituto Superior Técnico,
> > Universidade de Lisboa.
> >
> > ---
> > Changes in v2:
> > - Fix compilation errors and warnings
> > - Remove space idents
> > - Correct formatting
> >
> > João Mário Domingos (4):
> > RISC-V: Create unique identification for SoC PMU
> > RISC-V: Support CPUID for risc-v in perf
> > RISC-V: Added generic pmu-events mapfile
> > RISC-V: Added HiFive Unmatched PMU events
> >
> > arch/riscv/kernel/sbi.c | 3 +
> > drivers/perf/riscv_pmu.c | 18 ++++
> > drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++
> > tools/perf/arch/riscv/util/Build | 1 +
> > tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
> > tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
> > .../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
> > .../arch/riscv/sifive/u74/instructions.json | 92
> > +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json |
> > 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57
> > ++++++++++++ 10 files changed, 351 insertions(+)
> > create mode 100644 tools/perf/arch/riscv/util/header.c
> > create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> >
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-18 8:00 ` Atish Patra
@ 2021-11-22 14:57 ` João Mário Domingos
2021-11-22 16:26 ` Jessica Clarke
2021-11-23 5:24 ` Nikita Shubin
0 siblings, 2 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-22 14:57 UTC (permalink / raw)
To: Atish Patra
Cc: Nikita Shubin, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Atish Patra, Anup Patel, linux-riscv
On Thu, Nov 18, 2021 at 12:00:09AM -0800, Atish Patra wrote:
> On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> >
> > On Tue, 16 Nov 2021 15:48:08 +0000
> > João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> >
> > Hello Mario!
> >
> > Thank you for your patch series.
> >
> > I have reproduced your test with some u-boot dts tinkering, and got
> > similar results.
> >
> > However,
> >
> > >
> > > [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
> >
> > OpenSBI sscofpmf has been merged.
> >
> > > [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> > > [5]
> > > https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
> >
> > Is missing the adaptation for OpenSBI bitmap patch for
> > "raw-event-to-mhpmcounters".
>
> My patch was just an example and predates before the bitmap patch
> posted by Vincent.
> I will update the U-boot patch along with the next kernel version.
>
> >
> > > [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
> >
> > The link is broken.
> >
>
> Sorry. This should be
> https://github.com/atishp04/linux/tree/sbi_pmu_v4
>
> > > [4]
> > > http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> >
> > > [6]
> > > https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
> > >
> >
> > There is a version 2 submitted, and it won't apply as require rebasing
> > and some renaming.
> >
> > Please share your u-boot dts changes - they should be small and provide
> > a common base for this series.
> >
>
> Yes. That would be really helpful to have a DT path with all the
> entries for easier testing.
>
>
As the changes to the U-Boot are short I'm including them here, please tell me if I
should include them in other way. I merged my changes with Atish's own
patch to simplify the process.
diff -u b/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
--- b/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -141,6 +141,49 @@
#size-cells = <2>;
compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
ranges;
+ pmu {
+ compatible = "riscv,pmu";
+ pmu,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0x18
+ 0x00000000 0x00000200 0x18
+ 0x00000000 0x00000400 0x18
+ 0x00000000 0x00000800 0x18
+ 0x00000000 0x00001000 0x18
+ 0x00000000 0x00002000 0x18
+ 0x00000000 0x00004000 0x18
+ 0x00000000 0x00008000 0x18
+ 0x00000000 0x00010000 0x18
+ 0x00000000 0x00020000 0x18
+ 0x00000000 0x00040000 0x18
+ 0x00000000 0x00080000 0x18
+ 0x00000000 0x00100000 0x18
+ 0x00000000 0x00200000 0x18
+ 0x00000000 0x00400000 0x18
+ 0x00000000 0x00800000 0x18
+ 0x00000000 0x01000000 0x18
+ 0x00000000 0x02000000 0x18
+ 0x00000000 0x00000101 0x18
+ 0x00000000 0x00000201 0x18
+ 0x00000000 0x00000401 0x18
+ 0x00000000 0x00000801 0x18
+ 0x00000000 0x00001001 0x18
+ 0x00000000 0x00002001 0x18
+ 0x00000000 0x00004001 0x18
+ 0x00000000 0x00008001 0x18
+ 0x00000000 0x00010001 0x18
+ 0x00000000 0x00020001 0x18
+ 0x00000000 0x00040001 0x18
+ 0x00000000 0x00000102 0x18
+ 0x00000000 0x00000202 0x18
+ 0x00000000 0x00000402 0x18
+ 0x00000000 0x00000802 0x18
+ 0x00000000 0x00001002 0x18
+ 0x00000000 0x00002002 0x18>;
+ pmu,event-to-mhpmcounters = <0x05 0x06 0x18
+ 0x10009 0x10009 0x18>;
+ pmu,event-to-mhpmevent = <0x05 0x00000000 0x4000
+ 0x06 0x00000000 0x4001
+ 0x10008 0x00000000 0x102>;
+ };
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
> > Tested-by: Nikita Shubin <n.shubin@yadro.com>
> >
> > > Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> > >
> > > This work was developed at INESC-ID, Instituto Superior Técnico,
> > > Universidade de Lisboa.
> > >
> > > ---
> > > Changes in v2:
> > > - Fix compilation errors and warnings
> > > - Remove space idents
> > > - Correct formatting
>
>
>
> > >
> > > João Mário Domingos (4):
> > > RISC-V: Create unique identification for SoC PMU
> > > RISC-V: Support CPUID for risc-v in perf
> > > RISC-V: Added generic pmu-events mapfile
> > > RISC-V: Added HiFive Unmatched PMU events
> > >
> > > arch/riscv/kernel/sbi.c | 3 +
> > > drivers/perf/riscv_pmu.c | 18 ++++
> > > drivers/perf/riscv_pmu_sbi.c | 47 ++++++++++
> > > tools/perf/arch/riscv/util/Build | 1 +
> > > tools/perf/arch/riscv/util/header.c | 66 +++++++++++++
> > > tools/perf/pmu-events/arch/riscv/mapfile.csv | 15 +++
> > > .../pmu-events/arch/riscv/riscv-generic.json | 20 ++++
> > > .../arch/riscv/sifive/u74/instructions.json | 92
> > > +++++++++++++++++++ .../arch/riscv/sifive/u74/memory.json |
> > > 32 +++++++ .../arch/riscv/sifive/u74/microarch.json | 57
> > > ++++++++++++ 10 files changed, 351 insertions(+)
> > > create mode 100644 tools/perf/arch/riscv/util/header.c
> > > create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> > > create mode 100644
> > > tools/perf/pmu-events/arch/riscv/riscv-generic.json create mode
> > > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> > > create mode 100644
> > > tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode
> > > 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> > >
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> --
> Regards,
> Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events
2021-11-17 11:25 ` Nikita Shubin
@ 2021-11-22 15:24 ` João Mário Domingos
2021-11-23 5:19 ` Nikita Shubin
0 siblings, 1 reply; 23+ messages in thread
From: João Mário Domingos @ 2021-11-22 15:24 UTC (permalink / raw)
To: Nikita Shubin
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
On Wed, Nov 17, 2021 at 02:25:39PM +0300, Nikita Shubin wrote:
> On Tue, 16 Nov 2021 15:48:12 +0000
> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
>
> Hello Mario!
>
Hello Nikita!
> > + {
> > + "EventName": "UTLB_MISS",
> > + "EventCode": "0x0002002",
> > + "BriefDescription": "UTLB miss"
> > + }
>
> I don't see such thing in FU740 v1p3 manual - am i missing something ?
You are absolutelly right, there is no reference to the L2 cache
(Unified Cache) TLB misses event in the FU740 v1p3 manual. But
considering that the FU740 is composed of 1 S7 and 4 U74 cores, I used the U74 core complex
manual
[https://www.starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf]
as the source for events. Did you test the utlb_miss event, and does it
work in your board?
Best,
João Mário
>
> Yours,
> Nikita Shubin
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-22 14:57 ` João Mário Domingos
@ 2021-11-22 16:26 ` Jessica Clarke
2021-11-22 21:17 ` Atish Patra
2021-11-23 5:24 ` Nikita Shubin
1 sibling, 1 reply; 23+ messages in thread
From: Jessica Clarke @ 2021-11-22 16:26 UTC (permalink / raw)
To: João Mário Domingos
Cc: Atish Patra, Nikita Shubin, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Anup Patel, linux-riscv
On 22 Nov 2021, at 14:57, João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> On Thu, Nov 18, 2021 at 12:00:09AM -0800, Atish Patra wrote:
>> On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
>>>
>>> On Tue, 16 Nov 2021 15:48:08 +0000
>>> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
>>>
>>> Hello Mario!
>>>
>>> Thank you for your patch series.
>>>
>>> I have reproduced your test with some u-boot dts tinkering, and got
>>> similar results.
>>>
>>> However,
>>>
>>>>
>>>> [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
>>>
>>> OpenSBI sscofpmf has been merged.
>>>
>>>> [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
>>>> [5]
>>>> https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
>>>
>>> Is missing the adaptation for OpenSBI bitmap patch for
>>> "raw-event-to-mhpmcounters".
>>
>> My patch was just an example and predates before the bitmap patch
>> posted by Vincent.
>> I will update the U-boot patch along with the next kernel version.
>>
>>>
>>>> [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
>>>
>>> The link is broken.
>>>
>>
>> Sorry. This should be
>> https://github.com/atishp04/linux/tree/sbi_pmu_v4
>>
>>>> [4]
>>>> http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
>>>
>>>> [6]
>>>> https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
>>>>
>>>
>>> There is a version 2 submitted, and it won't apply as require rebasing
>>> and some renaming.
>>>
>>> Please share your u-boot dts changes - they should be small and provide
>>> a common base for this series.
>>>
>>
>> Yes. That would be really helpful to have a DT path with all the
>> entries for easier testing.
>>
>>
>
> As the changes to the U-Boot are short I'm including them here, please tell me if I
> should include them in other way. I merged my changes with Atish's own
> patch to simplify the process.
>
> diff -u b/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
> --- b/arch/riscv/dts/fu740-c000.dtsi
> +++ b/arch/riscv/dts/fu740-c000.dtsi
> @@ -141,6 +141,49 @@
> #size-cells = <2>;
> compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
> ranges;
> + pmu {
> + compatible = "riscv,pmu";
> + pmu,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0x18
> + 0x00000000 0x00000200 0x18
> + 0x00000000 0x00000400 0x18
> + 0x00000000 0x00000800 0x18
> + 0x00000000 0x00001000 0x18
> + 0x00000000 0x00002000 0x18
> + 0x00000000 0x00004000 0x18
> + 0x00000000 0x00008000 0x18
> + 0x00000000 0x00010000 0x18
> + 0x00000000 0x00020000 0x18
> + 0x00000000 0x00040000 0x18
> + 0x00000000 0x00080000 0x18
> + 0x00000000 0x00100000 0x18
> + 0x00000000 0x00200000 0x18
> + 0x00000000 0x00400000 0x18
> + 0x00000000 0x00800000 0x18
> + 0x00000000 0x01000000 0x18
> + 0x00000000 0x02000000 0x18
> + 0x00000000 0x00000101 0x18
> + 0x00000000 0x00000201 0x18
> + 0x00000000 0x00000401 0x18
> + 0x00000000 0x00000801 0x18
> + 0x00000000 0x00001001 0x18
> + 0x00000000 0x00002001 0x18
> + 0x00000000 0x00004001 0x18
> + 0x00000000 0x00008001 0x18
> + 0x00000000 0x00010001 0x18
> + 0x00000000 0x00020001 0x18
> + 0x00000000 0x00040001 0x18
> + 0x00000000 0x00000102 0x18
> + 0x00000000 0x00000202 0x18
> + 0x00000000 0x00000402 0x18
> + 0x00000000 0x00000802 0x18
> + 0x00000000 0x00001002 0x18
> + 0x00000000 0x00002002 0x18>;
> + pmu,event-to-mhpmcounters = <0x05 0x06 0x18
> + 0x10009 0x10009 0x18>;
> + pmu,event-to-mhpmevent = <0x05 0x00000000 0x4000
> + 0x06 0x00000000 0x4001
> + 0x10008 0x00000000 0x102>;
> + };
> plic0: interrupt-controller@c000000 {
> #interrupt-cells = <1>;
> compatible = "sifive,plic-1.0.0”;
I still highly disagree with this. The presence of the SBI PMU
extension is a property of the firmware, not the SoC, so it has no
place in /soc. Moreover its existence can be probed via the
sbi_probe_extension SBI call. It is already discoverable.
See my responses to Atish’s patches for more details.
Jess
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-22 16:26 ` Jessica Clarke
@ 2021-11-22 21:17 ` Atish Patra
2021-11-23 17:39 ` João Mário Domingos
0 siblings, 1 reply; 23+ messages in thread
From: Atish Patra @ 2021-11-22 21:17 UTC (permalink / raw)
To: Jessica Clarke
Cc: João Mário Domingos, Nikita Shubin, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Anup Patel, linux-riscv
On Mon, Nov 22, 2021 at 8:26 AM Jessica Clarke <jrtc27@jrtc27.com> wrote:
>
> On 22 Nov 2021, at 14:57, João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> > On Thu, Nov 18, 2021 at 12:00:09AM -0800, Atish Patra wrote:
> >> On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> >>>
> >>> On Tue, 16 Nov 2021 15:48:08 +0000
> >>> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> >>>
> >>> Hello Mario!
> >>>
> >>> Thank you for your patch series.
> >>>
> >>> I have reproduced your test with some u-boot dts tinkering, and got
> >>> similar results.
> >>>
> >>> However,
> >>>
> >>>>
> >>>> [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
> >>>
> >>> OpenSBI sscofpmf has been merged.
> >>>
> >>>> [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> >>>> [5]
> >>>> https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
> >>>
> >>> Is missing the adaptation for OpenSBI bitmap patch for
> >>> "raw-event-to-mhpmcounters".
> >>
> >> My patch was just an example and predates before the bitmap patch
> >> posted by Vincent.
> >> I will update the U-boot patch along with the next kernel version.
> >>
> >>>
> >>>> [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
> >>>
> >>> The link is broken.
> >>>
> >>
> >> Sorry. This should be
> >> https://github.com/atishp04/linux/tree/sbi_pmu_v4
> >>
> >>>> [4]
> >>>> http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> >>>
> >>>> [6]
> >>>> https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
> >>>>
> >>>
> >>> There is a version 2 submitted, and it won't apply as require rebasing
> >>> and some renaming.
> >>>
> >>> Please share your u-boot dts changes - they should be small and provide
> >>> a common base for this series.
> >>>
> >>
> >> Yes. That would be really helpful to have a DT path with all the
> >> entries for easier testing.
> >>
> >>
> >
> > As the changes to the U-Boot are short I'm including them here, please tell me if I
> > should include them in other way. I merged my changes with Atish's own
> > patch to simplify the process.
> >
> > diff -u b/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
> > --- b/arch/riscv/dts/fu740-c000.dtsi
> > +++ b/arch/riscv/dts/fu740-c000.dtsi
> > @@ -141,6 +141,49 @@
> > #size-cells = <2>;
> > compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
> > ranges;
> > + pmu {
> > + compatible = "riscv,pmu";
> > + pmu,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0x18
> > + 0x00000000 0x00000200 0x18
> > + 0x00000000 0x00000400 0x18
> > + 0x00000000 0x00000800 0x18
> > + 0x00000000 0x00001000 0x18
> > + 0x00000000 0x00002000 0x18
> > + 0x00000000 0x00004000 0x18
> > + 0x00000000 0x00008000 0x18
> > + 0x00000000 0x00010000 0x18
> > + 0x00000000 0x00020000 0x18
> > + 0x00000000 0x00040000 0x18
> > + 0x00000000 0x00080000 0x18
> > + 0x00000000 0x00100000 0x18
> > + 0x00000000 0x00200000 0x18
> > + 0x00000000 0x00400000 0x18
> > + 0x00000000 0x00800000 0x18
> > + 0x00000000 0x01000000 0x18
> > + 0x00000000 0x02000000 0x18
> > + 0x00000000 0x00000101 0x18
> > + 0x00000000 0x00000201 0x18
> > + 0x00000000 0x00000401 0x18
> > + 0x00000000 0x00000801 0x18
> > + 0x00000000 0x00001001 0x18
> > + 0x00000000 0x00002001 0x18
> > + 0x00000000 0x00004001 0x18
> > + 0x00000000 0x00008001 0x18
> > + 0x00000000 0x00010001 0x18
> > + 0x00000000 0x00020001 0x18
> > + 0x00000000 0x00040001 0x18
> > + 0x00000000 0x00000102 0x18
> > + 0x00000000 0x00000202 0x18
> > + 0x00000000 0x00000402 0x18
> > + 0x00000000 0x00000802 0x18
> > + 0x00000000 0x00001002 0x18
> > + 0x00000000 0x00002002 0x18>;
> > + pmu,event-to-mhpmcounters = <0x05 0x06 0x18
> > + 0x10009 0x10009 0x18>;
> > + pmu,event-to-mhpmevent = <0x05 0x00000000 0x4000
> > + 0x06 0x00000000 0x4001
> > + 0x10008 0x00000000 0x102>;
> > + };
> > plic0: interrupt-controller@c000000 {
> > #interrupt-cells = <1>;
> > compatible = "sifive,plic-1.0.0”;
>
> I still highly disagree with this. The presence of the SBI PMU
> extension is a property of the firmware, not the SoC, so it has no
> place in /soc. Moreover its existence can be probed via the
> sbi_probe_extension SBI call. It is already discoverable.
>
> See my responses to Atish’s patches for more details.
Hi Jessica,
I am working on revising the PMU series based on your feedback.
The diff proposed here will go into the device tree in U-Boot meant to be used
for firmware. Firmware should remove these DT properties before
jumping to the Linux kernel
Currently OpenSBI does this as well.
> Jess
>
--
Regards,
Atish
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events
2021-11-22 15:24 ` João Mário Domingos
@ 2021-11-23 5:19 ` Nikita Shubin
0 siblings, 0 replies; 23+ messages in thread
From: Nikita Shubin @ 2021-11-23 5:19 UTC (permalink / raw)
To: João Mário Domingos
Cc: palmer, paul.walmsley, aou, atish.patra, anup.patel, linux-riscv
Hello Mario!
On Mon, 22 Nov 2021 15:24:08 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> On Wed, Nov 17, 2021 at 02:25:39PM +0300, Nikita Shubin wrote:
> > On Tue, 16 Nov 2021 15:48:12 +0000
> > João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> >
> > Hello Mario!
> >
> Hello Nikita!
> > > + {
> > > + "EventName": "UTLB_MISS",
> > > + "EventCode": "0x0002002",
> > > + "BriefDescription": "UTLB miss"
> > > + }
> >
> > I don't see such thing in FU740 v1p3 manual - am i missing
> > something ?
> You are absolutelly right, there is no reference to the L2 cache
> (Unified Cache) TLB misses event in the FU740 v1p3 manual. But
> considering that the FU740 is composed of 1 S7 and 4 U74 cores, I
> used the U74 core complex manual
> [https://www.starfivetech.com/uploads/u74_core_complex_manual_21G1.pdf]
> as the source for events. Did you test the utlb_miss event, and does
> it work in your board?
Thank you for pointing this out, it works indeed. Unfortunately not the
first inexactness in the FU740 v1p3 manual.
>
> Best,
> João Mário
> >
> > Yours,
> > Nikita Shubin
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-22 14:57 ` João Mário Domingos
2021-11-22 16:26 ` Jessica Clarke
@ 2021-11-23 5:24 ` Nikita Shubin
1 sibling, 0 replies; 23+ messages in thread
From: Nikita Shubin @ 2021-11-23 5:24 UTC (permalink / raw)
To: João Mário Domingos
Cc: Atish Patra, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Atish Patra, Anup Patel, linux-riscv
Hello Mario!
On Mon, 22 Nov 2021 14:57:52 +0000
João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
>
> As the changes to the U-Boot are short I'm including them here,
> please tell me if I should include them in other way. I merged my
> changes with Atish's own patch to simplify the process.
>
> diff -u b/arch/riscv/dts/fu740-c000.dtsi
> b/arch/riscv/dts/fu740-c000.dtsi --- b/arch/riscv/dts/fu740-c000.dtsi
> +++ b/arch/riscv/dts/fu740-c000.dtsi
> @@ -141,6 +141,49 @@
> #size-cells = <2>;
> compatible = "sifive,fu740-c000", "sifive,fu740",
> "simple-bus"; ranges;
> + pmu {
> + compatible = "riscv,pmu";
> + pmu,raw-event-to-mhpmcounters = <0x00000000
> 0x00000100 0x18
> + 0x00000000
> 0x00000200 0x18
> + 0x00000000
> 0x00000400 0x18
> + 0x00000000
> 0x00000800 0x18
> + 0x00000000
> 0x00001000 0x18
> + 0x00000000
> 0x00002000 0x18
> + 0x00000000
> 0x00004000 0x18
> + 0x00000000
> 0x00008000 0x18
> + 0x00000000
> 0x00010000 0x18
> + 0x00000000
> 0x00020000 0x18
> + 0x00000000
> 0x00040000 0x18
> + 0x00000000
> 0x00080000 0x18
> + 0x00000000
> 0x00100000 0x18
> + 0x00000000
> 0x00200000 0x18
> + 0x00000000
> 0x00400000 0x18
> + 0x00000000
> 0x00800000 0x18
> + 0x00000000
> 0x01000000 0x18
> + 0x00000000
> 0x02000000 0x18
> + 0x00000000
> 0x00000101 0x18
> + 0x00000000
> 0x00000201 0x18
> + 0x00000000
> 0x00000401 0x18
> + 0x00000000
> 0x00000801 0x18
> + 0x00000000
> 0x00001001 0x18
> + 0x00000000
> 0x00002001 0x18
> + 0x00000000
> 0x00004001 0x18
> + 0x00000000
> 0x00008001 0x18
> + 0x00000000
> 0x00010001 0x18
> + 0x00000000
> 0x00020001 0x18
> + 0x00000000
> 0x00040001 0x18
> + 0x00000000
> 0x00000102 0x18
> + 0x00000000
> 0x00000202 0x18
> + 0x00000000
> 0x00000402 0x18
> + 0x00000000
> 0x00000802 0x18
> + 0x00000000
> 0x00001002 0x18
> + 0x00000000
> 0x00002002 0x18>;
> + pmu,event-to-mhpmcounters = <0x05 0x06 0x18
> + 0x10009 0x10009
> 0x18>;
> + pmu,event-to-mhpmevent = <0x05 0x00000000
> 0x4000
> + 0x06 0x00000000
> 0x4001
> + 0x10008 0x00000000
> 0x102>;
> + };
Well, i definitely thought it was shorter...
After applying Vincent Chen patches:
https://patchwork.ozlabs.org/project/opensbi/patch/20211110050153.26935-1-vincent.chen@sifive.com/
My looks like:
diff --git a/arch/riscv/dts/fu740-c000.dtsi
b/arch/riscv/dts/fu740-c000.dtsi index 649efe400a..6a155b2b86 100644
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -141,6 +141,17 @@
#size-cells = <2>;
compatible = "sifive,fu740-c000", "sifive,fu740",
"simple-bus"; ranges;
+ pmu {
+ compatible = "riscv,pmu";
+ riscv,raw-event-to-mhpmcounters = <0x00000000
0x3ffff00 0x0 0x0 0x18
+ 0x00000000
0x7ff01 0x0 0x1 0x18
+ 0x00000000
0x3f02 0x0 0x2 0x18>;
+ riscv,event-to-mhpmcounters = <0x05 0x06 0x18
+ 0x10009 0x10009
0x18>;
+ riscv,event-to-mhpmevent = <0x05 0x00000000
0x4000
+ 0x06 0x00000000 0x4001
+ 0x10008 0x00000000
0x102>;
+ };
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
Shorter indeed, but surely less readable.
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched
2021-11-22 21:17 ` Atish Patra
@ 2021-11-23 17:39 ` João Mário Domingos
0 siblings, 0 replies; 23+ messages in thread
From: João Mário Domingos @ 2021-11-23 17:39 UTC (permalink / raw)
To: Atish Patra
Cc: Jessica Clarke, Nikita Shubin, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Anup Patel, linux-riscv
On Mon, Nov 22, 2021 at 01:17:33PM -0800, Atish Patra wrote:
> On Mon, Nov 22, 2021 at 8:26 AM Jessica Clarke <jrtc27@jrtc27.com> wrote:
> >
> > On 22 Nov 2021, at 14:57, João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> > > On Thu, Nov 18, 2021 at 12:00:09AM -0800, Atish Patra wrote:
> > >> On Wed, Nov 17, 2021 at 4:25 AM Nikita Shubin <nikita.shubin@maquefel.me> wrote:
> > >>>
> > >>> On Tue, 16 Nov 2021 15:48:08 +0000
> > >>> João Mário Domingos <joao.mario@tecnico.ulisboa.pt> wrote:
> > >>>
> > >>> Hello Mario!
> > >>>
> > >>> Thank you for your patch series.
> > >>>
> > >>> I have reproduced your test with some u-boot dts tinkering, and got
> > >>> similar results.
> > >>>
> > >>> However,
> > >>>
> > >>>>
> > >>>> [1] https://github.com/atishp04/opensbi/tree/pmu_sscofpmf_v2
> > >>>
> > >>> OpenSBI sscofpmf has been merged.
> > >>>
> > >>>> [2] https://github.com/atishp04/u-boot/tree/hifive_unmatched_dt_pmu
> > >>>> [5]
> > >>>> https://github.com/atishp04/u-boot/blob/hifive_unmatched_dt_pmu/arch/riscv/dts/fu740-c000.dtsi
> > >>>
> > >>> Is missing the adaptation for OpenSBI bitmap patch for
> > >>> "raw-event-to-mhpmcounters".
> > >>
> > >> My patch was just an example and predates before the bitmap patch
> > >> posted by Vincent.
> > >> I will update the U-boot patch along with the next kernel version.
> > >>
> > >>>
> > >>>> [3] https://github.com/atishp04/linux/tree/riscv_pmu_v4
> > >>>
> > >>> The link is broken.
> > >>>
> > >>
> > >> Sorry. This should be
> > >> https://github.com/atishp04/linux/tree/sbi_pmu_v4
> > >>
> > >>>> [4]
> > >>>> http://lists.infradead.org/pipermail/linux-riscv/2021-October/009408.html
> > >>>
> > >>>> [6]
> > >>>> https://patchwork.ozlabs.org/project/opensbi/patch/20211105013301.27656-1-vincent.chen@sifive.com/
> > >>>>
> > >>>
> > >>> There is a version 2 submitted, and it won't apply as require rebasing
> > >>> and some renaming.
> > >>>
> > >>> Please share your u-boot dts changes - they should be small and provide
> > >>> a common base for this series.
> > >>>
> > >>
> > >> Yes. That would be really helpful to have a DT path with all the
> > >> entries for easier testing.
> > >>
> > >>
> > >
> > > As the changes to the U-Boot are short I'm including them here, please tell me if I
> > > should include them in other way. I merged my changes with Atish's own
> > > patch to simplify the process.
> > >
> > > diff -u b/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
> > > --- b/arch/riscv/dts/fu740-c000.dtsi
> > > +++ b/arch/riscv/dts/fu740-c000.dtsi
> > > @@ -141,6 +141,49 @@
> > > #size-cells = <2>;
> > > compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
> > > ranges;
> > > + pmu {
> > > + compatible = "riscv,pmu";
> > > + pmu,raw-event-to-mhpmcounters = <0x00000000 0x00000100 0x18
> > > + 0x00000000 0x00000200 0x18
> > > + 0x00000000 0x00000400 0x18
> > > + 0x00000000 0x00000800 0x18
> > > + 0x00000000 0x00001000 0x18
> > > + 0x00000000 0x00002000 0x18
> > > + 0x00000000 0x00004000 0x18
> > > + 0x00000000 0x00008000 0x18
> > > + 0x00000000 0x00010000 0x18
> > > + 0x00000000 0x00020000 0x18
> > > + 0x00000000 0x00040000 0x18
> > > + 0x00000000 0x00080000 0x18
> > > + 0x00000000 0x00100000 0x18
> > > + 0x00000000 0x00200000 0x18
> > > + 0x00000000 0x00400000 0x18
> > > + 0x00000000 0x00800000 0x18
> > > + 0x00000000 0x01000000 0x18
> > > + 0x00000000 0x02000000 0x18
> > > + 0x00000000 0x00000101 0x18
> > > + 0x00000000 0x00000201 0x18
> > > + 0x00000000 0x00000401 0x18
> > > + 0x00000000 0x00000801 0x18
> > > + 0x00000000 0x00001001 0x18
> > > + 0x00000000 0x00002001 0x18
> > > + 0x00000000 0x00004001 0x18
> > > + 0x00000000 0x00008001 0x18
> > > + 0x00000000 0x00010001 0x18
> > > + 0x00000000 0x00020001 0x18
> > > + 0x00000000 0x00040001 0x18
> > > + 0x00000000 0x00000102 0x18
> > > + 0x00000000 0x00000202 0x18
> > > + 0x00000000 0x00000402 0x18
> > > + 0x00000000 0x00000802 0x18
> > > + 0x00000000 0x00001002 0x18
> > > + 0x00000000 0x00002002 0x18>;
> > > + pmu,event-to-mhpmcounters = <0x05 0x06 0x18
> > > + 0x10009 0x10009 0x18>;
> > > + pmu,event-to-mhpmevent = <0x05 0x00000000 0x4000
> > > + 0x06 0x00000000 0x4001
> > > + 0x10008 0x00000000 0x102>;
> > > + };
> > > plic0: interrupt-controller@c000000 {
> > > #interrupt-cells = <1>;
> > > compatible = "sifive,plic-1.0.0”;
> >
> > I still highly disagree with this. The presence of the SBI PMU
> > extension is a property of the firmware, not the SoC, so it has no
> > place in /soc. Moreover its existence can be probed via the
> > sbi_probe_extension SBI call. It is already discoverable.
> >
> > See my responses to Atish’s patches for more details.
> Hi Jessica,
> I am working on revising the PMU series based on your feedback.
> The diff proposed here will go into the device tree in U-Boot meant to be used
> for firmware. Firmware should remove these DT properties before
> jumping to the Linux kernel
> Currently OpenSBI does this as well.
>
Hi Atish and Jessica, I've seen your responses in Atish's patches and I
will update this series in accordance with the upcoming Atish's
changes.
From what I can anticipate the modifications will be minor, if
any, as this relates mainly to U-boot, as Atish stated.
>
> > Jess
> >
>
>
> --
> Regards,
> Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2021-11-23 17:39 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-09 10:25 [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched João Mário Domingos
2021-11-09 10:25 ` [PATCH 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-15 8:23 ` Nikita Shubin
2021-11-16 15:54 ` João Mário Domingos
2021-11-09 10:25 ` [PATCH 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-09 10:25 ` [PATCH 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-09 10:25 ` [PATCH 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-10 13:55 ` [PATCH 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-16 15:48 ` [PATCH v2 " João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 1/4] RISC-V: Create unique identification for SoC PMU João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 2/4] RISC-V: Support CPUID for risc-v in perf João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 3/4] RISC-V: Added generic pmu-events mapfile João Mário Domingos
2021-11-16 15:48 ` [PATCH v2 4/4] RISC-V: Added HiFive Unmatched PMU events João Mário Domingos
2021-11-17 11:25 ` Nikita Shubin
2021-11-22 15:24 ` João Mário Domingos
2021-11-23 5:19 ` Nikita Shubin
2021-11-17 12:25 ` [PATCH v2 0/4] Introduce pmu-events support for HiFive Unmatched Nikita Shubin
2021-11-18 8:00 ` Atish Patra
2021-11-22 14:57 ` João Mário Domingos
2021-11-22 16:26 ` Jessica Clarke
2021-11-22 21:17 ` Atish Patra
2021-11-23 17:39 ` João Mário Domingos
2021-11-23 5:24 ` Nikita Shubin
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