From: firstname.lastname@example.org To: Peter Maydell <email@example.com> Cc: "Michael S. Tsirkin" <firstname.lastname@example.org>, Radoslaw Biernacki <email@example.com>, QEMU Developers <firstname.lastname@example.org>, qemu-arm <email@example.com>, Igor Mammedov <firstname.lastname@example.org>, Leif Lindholm <email@example.com> Subject: Re: [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Date: Tue, 06 Jul 2021 08:46:42 -0400 [thread overview] Message-ID: <firstname.lastname@example.org> (raw) In-Reply-To: <CAFEAcA-xC_v2z=QaD=_dkFWx2Hr+UFd0h_YTtSi6MNPhk6-Sbg@mail.gmail.com> On Tue, 2021-07-06 at 10:19 +0100, Peter Maydell wrote: > On Tue, 6 Jul 2021 at 04:25, <email@example.com> wrote: > > On Mon, 2021-07-05 at 20:47 -0400, firstname.lastname@example.org wrote: > > > On Mon, 2021-07-05 at 15:54 +0100, Peter Maydell wrote: > > > > I missed this the first time around, but I don't think this is > > > > right. > > > > Different CPUs could have different GICR_PROPBASER values, so > > > > checking > > > > against just one of them is wrong. The pseudocode only tests > > > > LPIOutOfRange() > > > > which is documented as testing "larger than GICD_TYPER.IDbits > > > > or > > > > not > > > > in > > > > the LPI range and not 1023". So I don't think we should be > > > > looking > > > > at the GICR_PROPBASER field here. > > > > > > > > More generally, "s->gicv3->cpu->something" is usually going to > > > > be > > > > wrong, because it is implicitly looking at CPU 0; often either > > > > there > > > > should be something else telling is which CPU to use (as in > > > > &s->gicv3->cpu[rdbase] where the CTE told us which > > > > redistributor), > > > > or we might need to operate on all CPUs/redistributors. The > > > > only > > > > exception is where we can guarantee that all the CPUs are the > > > > same > > > > (eg when looking at GICR_TYPER.PLPIS.) > > Please ignore my last comment. > > > > To address this scenario,i think the feasible option would be to > > call > > get_cte() to get the rdbase corresponding to icid value passed to > > mapti > > command.Since each icid is mapped to a rdbase(by virtue of calling > > MAPC > > command),if the collection table has a valid mapping for this icid > > we > > continue processing this MAPTI command using &s->gicv3->cpu[rdbase] > > applicable propbaser value to validate idbits, else return without > > further processing. > > But the pseudocode for MAPTI does not say anywhere that we should > be checking the pIntID against any CPU's GICR_PROPBASER field. > It is checked only by the checks in LPIOutOfRange(), which tests: > * is it larger than permitted by GICD_TYPER.IDbits > * is it not in the LPI range and not 1023 > > Checking whether the intID is too big and would cause us to index > off the end of the redistributor's configuration table should be done > later, only when the ITS actually sends the interrupt to a particular > redistributor, I think. > > (You can't rely on the guest having done the MAPC before the MAPTI; > and in any case the guest could choose to do a MAPC to a different > redistributor after it's done the MAPTI.) > > thanks > -- PMM We already have the "intID too big check" in place within the redistributor processing when ITS sends the interrupt trigger. "the LPI range and not 1023" is also handled in this function,but for validating "is it larger than permitted by GICD_TYPER.IDbits",the source of GICD_TYPER.IDbits is GICR_PROPBASER because we pick up min of GICR_PROPBASER.IDbits and GICD_TYPER.IDBits. If we are to not use gicr_propbaser,then are we good to just accept the intID value here since we are validating the same during interrupt processing?
next prev parent reply other threads:[~2021-07-06 12:48 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-30 15:31 [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Shashi Mallela 2021-06-30 15:31 ` [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework Shashi Mallela 2021-07-05 14:58 ` Peter Maydell 2021-07-05 15:55 ` shashi.mallela 2021-07-05 16:25 ` Peter Maydell 2021-07-05 17:04 ` shashi.mallela 2021-07-05 18:58 ` Peter Maydell 2021-07-07 2:08 ` shashi.mallela 2021-07-06 7:44 ` Eric Auger 2021-07-07 2:06 ` shashi.mallela 2021-06-30 15:31 ` [PATCH v5 02/10] hw/intc: GICv3 ITS register definitions added Shashi Mallela 2021-07-06 9:29 ` Eric Auger 2021-07-08 17:27 ` Eric Auger 2021-08-05 21:14 ` shashi.mallela 2021-06-30 15:31 ` [PATCH v5 03/10] hw/intc: GICv3 ITS command queue framework Shashi Mallela 2021-07-06 9:31 ` Eric Auger 2021-06-30 15:31 ` [PATCH v5 04/10] hw/intc: GICv3 ITS Command processing Shashi Mallela 2021-07-05 14:07 ` Peter Maydell 2021-07-06 9:27 ` Eric Auger 2021-07-07 2:02 ` shashi.mallela 2021-07-05 14:54 ` Peter Maydell 2021-07-06 0:47 ` shashi.mallela 2021-07-06 3:25 ` shashi.mallela 2021-07-06 9:19 ` Peter Maydell 2021-07-06 12:46 ` shashi.mallela [this message] 2021-07-06 13:27 ` Peter Maydell 2021-07-07 2:08 ` shashi.mallela 2021-07-06 10:04 ` Eric Auger 2021-07-06 10:07 ` Peter Maydell 2021-07-06 10:05 ` Eric Auger 2021-06-30 15:31 ` [PATCH v5 05/10] hw/intc: GICv3 ITS Feature enablement Shashi Mallela 2021-07-05 14:20 ` Peter Maydell 2021-06-30 15:31 ` [PATCH v5 06/10] hw/intc: GICv3 redistributor ITS processing Shashi Mallela 2021-07-05 14:43 ` Peter Maydell 2021-06-30 15:31 ` [PATCH v5 07/10] hw/arm/sbsa-ref: add ITS support in SBSA GIC Shashi Mallela 2021-07-05 14:59 ` Peter Maydell 2021-06-30 15:31 ` [PATCH v5 08/10] tests/data/acpi/virt: Add IORT files for ITS Shashi Mallela 2021-06-30 15:31 ` [PATCH v5 09/10] hw/arm/virt: add ITS support in virt GIC Shashi Mallela 2021-06-30 15:31 ` [PATCH v5 10/10] tests/data/acpi/virt: Update IORT files for ITS Shashi Mallela 2021-07-05 15:02 ` Peter Maydell 2021-07-05 15:05 ` [PATCH v5 00/10] GICv3 LPI and ITS feature implementation Peter Maydell
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