[PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  184 +++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   80 ++++++++++++
 2 files changed, 264 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 0000000..2db68b2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,184 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+	compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <20 2 0 0>;
+	pcie@0 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <20 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 40 1 0 0
+			0000 0 0 2 &mpic 1 1 0 0
+			0000 0 0 3 &mpic 2 1 0 0
+			0000 0 0 4 &mpic 3 1 0 0
+			>;
+	};
+};
+
+&rio {
+	compatible = "fsl,srio";
+	interrupts = <16 2 1 11>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	port1 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		cell-index = <1>;
+	};
+
+	port2 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		cell-index = <2>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+
+	soc-sram-error {
+		compatible = "fsl,soc-sram-error";
+		interrupts = <16 2 1 2>;
+	};
+
+	corenet-law@0 {
+		compatible = "fsl,corenet-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <32>;
+	};
+
+	ddr1: memory-controller@8000 {
+		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+		reg = <0x8000 0x1000>;
+		interrupts = <16 2 1 8>;
+	};
+
+	ddr2: memory-controller@9000 {
+		compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
+		reg = <0x9000 0x1000>;
+		interrupts = <16 2 1 9>;
+	};
+
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+		reg = <0x10000 0x1000
+		       0x11000 0x1000>;
+		interrupts = <16 2 1 4
+			      16 2 1 5>;
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,corenet-cf";
+		reg = <0x18000 0x1000>;
+		interrupts = <16 2 1 0>;
+		fsl,ccf-num-csdids = <32>;
+		fsl,ccf-num-snoopids = <32>;
+	};
+
+	iommu@20000 {
+		compatible = "fsl,pamu-v1.0", "fsl,pamu";
+		reg = <0x20000 0x4000>;
+		interrupts = <
+			24 2 0 0
+			16 2 1 1>;
+	};
+
+/include/ "qoriq-mpic.dtsi"
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,b4860-device-config";
+		reg = <0xe0000 0xe00>;
+		fsl,has-rstcr;
+		fsl,liodn-bits = <12>;
+	};
+
+	clockgen: global-utilities@e1000 {
+		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
+		reg = <0xe1000 0x1000>;
+	};
+
+	rcpm: global-utilities@e2000 {
+		compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2";
+		reg = <0xe2000 0x1000>;
+	};
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+
+/include/ "qonverge-usb2-dr-0.dtsi"
+	usb0: usb@210000 {
+		compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+	};
+
+/include/ "qoriq-espi-0.dtsi"
+	spi@110000 {
+		fsl,espi-num-chipselects = <4>;
+	};
+
+/include/ "qoriq-esdhc-0.dtsi"
+	sdhc@114000 {
+		sdhci,auto-cmd12;
+	};
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+
+	L2: l2-cache-controller@c20000 {
+		next-level-cache = <&cpc>;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 0000000..33bc600
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,80 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+/ {
+	compatible = "fsl,B4860";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		ccsr = &soc;
+
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		pci0 = &pci0;
+		dma0 = &dma0;
+		dma1 = &dma1;
+		sdhc = &sdhc;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			next-level-cache = <&L2>;
+		};
+		PowerPC,e6500@1 {
+			device_type = "cpu";
+			reg = <2 3>;
+			next-level-cache = <&L2>;
+		};
+		PowerPC,e6500@2 {
+			device_type = "cpu";
+			reg = <4 5>;
+			next-level-cache = <&L2>;
+		};
+		PowerPC,e6500@3 {
+			device_type = "cpu";
+			reg = <6 7>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.7.6.GIT

[PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/boot/dts/b4860qds.dts |  178 ++++++++++++++++++++++++++++++++++++
 1 files changed, 178 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/b4860qds.dts

diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 0000000..ae6ac05
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,178 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/b4860si-pre.dtsi"
+
+/ {
+	model = "fsl,B4860QDS";
+	compatible = "fsl,B4860QDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	ifc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x2000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000
+			  2 0 0xf 0xff800000 0x00010000
+			  3 0 0xf 0xffdf0000 0x00008000>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,ifc-nand";
+			reg = <0x2 0x0 0x10000>;
+
+			partition@0 {
+				/* This location must not be altered  */
+				/* 1MB for u-boot Bootloader Image */
+				reg = <0x0 0x00100000>;
+				label = "NAND U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 1MB for DTB Image */
+				reg = <0x00100000 0x00100000>;
+				label = "NAND DTB Image";
+			};
+
+			partition@200000 {
+				/* 10MB for Linux Kernel Image */
+				reg = <0x00200000 0x00A00000>;
+				label = "NAND Linux Kernel Image";
+			};
+
+			partition@c00000 {
+				/* 500MB for Root file System Image */
+				reg = <0x00c00000 0x1F400000>;
+				label = "NAND RFS Image";
+			};
+		};
+
+		board-control@3,0 {
+			compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
+			reg = <3 0 0x300>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		spi@110000 {
+			flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "sst,sst25wf040";
+				reg = <0>;
+				spi-max-frequency = <40000000>; /* input clock */
+			};
+		};
+
+		sdhc@114000 {
+			status = "disabled";
+		};
+
+		i2c@118000 {
+			eeprom@50 {
+				compatible = "at24,24c64";
+				reg = <0x50>;
+			};
+			eeprom@51 {
+				compatible = "at24,24c256";
+				reg = <0x51>;
+			};
+			eeprom@53 {
+				compatible = "at24,24c256";
+				reg = <0x53>;
+			};
+			eeprom@57 {
+				compatible = "at24,24c256";
+				reg = <0x57>;
+			};
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				interrupts = <0x1 0x1 0 0>;
+			};
+		};
+
+		usb@210000 {
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+	};
+
+	pci0: pcie@ffe200000 {
+		reg = <0xf 0xfe200000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+	rio: rapidio@ffe0c0000 {
+		reg = <0xf 0xfe0c0000 0 0x11000>;
+
+		port1 {
+			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+		};
+		port2 {
+			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+		};
+	};
+
+};
+
+/include/ "fsl/b4860si-post.dtsi"
-- 
1.7.6.GIT

[PATCH 3/6] powerpc/fsl-booke: Add initial silicon device tree files for B4420QDS

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |  151 +++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   70 ++++++++++++
 2 files changed, 221 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 0000000..e45d605
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,151 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	compatible = "fsl,ifc", "simple-bus";
+	interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+	compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
+	device_type = "pci";
+	#size-cells = <2>;
+	#address-cells = <3>;
+	bus-range = <0x0 0xff>;
+	interrupts = <20 2 0 0>;
+	pcie@0 {
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		device_type = "pci";
+		interrupts = <20 2 0 0>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <
+			/* IDSEL 0x0 */
+			0000 0 0 1 &mpic 40 1 0 0
+			0000 0 0 2 &mpic 1 1 0 0
+			0000 0 0 3 &mpic 2 1 0 0
+			0000 0 0 4 &mpic 3 1 0 0
+			>;
+	};
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	device_type = "soc";
+	compatible = "simple-bus";
+
+	soc-sram-error {
+		compatible = "fsl,soc-sram-error";
+		interrupts = <16 2 1 2>;
+	};
+
+	corenet-law@0 {
+		compatible = "fsl,corenet-law";
+		reg = <0x0 0x1000>;
+		fsl,num-laws = <32>;
+	};
+
+	ddr1: memory-controller@8000 {
+		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+		reg = <0x8000 0x1000>;
+		interrupts = <16 2 1 8>;
+	};
+
+	cpc: l3-cache-controller@10000 {
+		compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+		reg = <0x10000 0x1000>;
+		interrupts = <16 2 1 4>;
+	};
+
+	corenet-cf@18000 {
+		compatible = "fsl,corenet-cf";
+		reg = <0x18000 0x1000>;
+		interrupts = <16 2 1 0>;
+		fsl,ccf-num-csdids = <32>;
+		fsl,ccf-num-snoopids = <32>;
+	};
+
+	iommu@20000 {
+		compatible = "fsl,pamu";
+		reg = <0x20000 0x4000>;
+		interrupts = <
+			24 2 0 0
+			16 2 1 1>;
+	};
+
+/include/ "qoriq-mpic.dtsi"
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,b4420-device-config";
+		reg = <0xe0000 0xe00>;
+		fsl,has-rstcr;
+		fsl,liodn-bits = <12>;
+	};
+
+	rcpm: global-utilities@e2000 {
+		compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2";
+		reg = <0xe2000 0x1000>;
+	};
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+
+/include/ "qonverge-usb2-dr-0.dtsi"
+	usb0: usb@210000 {
+		compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+	};
+
+/include/ "qoriq-espi-0.dtsi"
+	spi@110000 {
+		fsl,espi-num-chipselects = <4>;
+	};
+
+/include/ "qoriq-esdhc-0.dtsi"
+	sdhc@114000 {
+		sdhci,auto-cmd12;
+	};
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+
+	L2: l2-cache-controller@c20000 {
+		next-level-cache = <&cpc>;
+	};
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 0000000..c1ade3b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,70 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+/ {
+	compatible = "fsl,B4420";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	aliases {
+		ccsr = &soc;
+
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		serial3 = &serial3;
+		pci0 = &pci0;
+		dma0 = &dma0;
+		dma1 = &dma1;
+		sdhc = &sdhc;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,e6500@0 {
+			device_type = "cpu";
+			reg = <0 1>;
+			next-level-cache = <&L2>;
+		};
+		PowerPC,e6500@1 {
+			device_type = "cpu";
+			reg = <2 3>;
+			next-level-cache = <&L2>;
+		};
+	};
+};
-- 
1.7.6.GIT

[PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/boot/dts/b4420qds.dts |  168 ++++++++++++++++++++++++++++++++++++
 1 files changed, 168 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/b4420qds.dts

diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
new file mode 100644
index 0000000..3152f8c
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -0,0 +1,168 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4420si-pre.dtsi"
+
+/ {
+	model = "fsl,B4420QDS";
+	compatible = "fsl,B4420QDS";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&mpic>;
+
+	ifc: localbus@ffe124000 {
+		reg = <0xf 0xfe124000 0 0x2000>;
+		ranges = <0 0 0xf 0xe8000000 0x08000000
+			  2 0 0xf 0xff800000 0x00010000
+			  3 0 0xf 0xffdf0000 0x00008000>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,ifc-nand";
+			reg = <0x2 0x0 0x10000>;
+
+			partition@0 {
+				/* This location must not be altered  */
+				/* 1MB for u-boot Bootloader Image */
+				reg = <0x0 0x00100000>;
+				label = "NAND U-Boot Image";
+				read-only;
+			};
+
+			partition@100000 {
+				/* 1MB for DTB Image */
+				reg = <0x00100000 0x00100000>;
+				label = "NAND DTB Image";
+			};
+
+			partition@200000 {
+				/* 10MB for Linux Kernel Image */
+				reg = <0x00200000 0x00A00000>;
+				label = "NAND Linux Kernel Image";
+			};
+
+			partition@c00000 {
+				/* 500MB for Root file System Image */
+				reg = <0x00c00000 0x1F400000>;
+				label = "NAND RFS Image";
+			};
+		};
+
+		board-control@3,0 {
+			compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
+			reg = <3 0 0x300>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+	};
+
+	soc: soc@ffe000000 {
+		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+		reg = <0xf 0xfe000000 0 0x00001000>;
+		spi@110000 {
+			flash@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "sst,sst25wf040";
+				reg = <0>;
+				spi-max-frequency = <40000000>; /* input clock */
+			};
+		};
+
+		sdhc@114000 {
+			/*Disabled as there is no sdhc connector on B4420QDS board*/
+			status = "disabled";
+		};
+
+		i2c@118000 {
+			eeprom@50 {
+				compatible = "at24,24c64";
+				reg = <0x50>;
+			};
+			eeprom@51 {
+				compatible = "at24,24c256";
+				reg = <0x51>;
+			};
+			eeprom@53 {
+				compatible = "at24,24c256";
+				reg = <0x53>;
+			};
+			eeprom@57 {
+				compatible = "at24,24c256";
+				reg = <0x57>;
+			};
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				interrupts = <0x1 0x1 0 0>;
+			};
+		};
+
+		usb@210000 {
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+	};
+
+	pci0: pcie@ffe200000 {
+		reg = <0xf 0xfe200000 0 0x10000>;
+		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+		pcie@0 {
+			ranges = <0x02000000 0 0xe0000000
+				  0x02000000 0 0xe0000000
+				  0 0x20000000
+
+				  0x01000000 0 0x00000000
+				  0x01000000 0 0x00000000
+				  0 0x00010000>;
+		};
+	};
+
+};
+
+/include/ "fsl/b4420si-post.dtsi"
-- 
1.7.6.GIT

[PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Shaveta Leekha]

- Add support for B4 board's personalities in board file
  b4_qds.c, It is common for B4 personalities B4860 and B4420QDS
- Add B4QDS support in Kconfig and Makefile

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor,
with following major features:

    - Four dual-threaded e6500 Power Architecture processors
      organized in one cluster-each core runs up to 1.8 GHz
    - Two DDR3/3L controllers for high-speed memory interface each
      runs at up to 1866.67 MHz
    - CoreNet fabric that fully supports coherency using MESI protocol
      between the e6500 cores, SC3900 FVP cores, memories and
      external interfaces.
    - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3 and RMAN
    - Large internal cache memory with snooping and stashing capabilities
    - Sixteen 10-GHz SerDes lanes that serve:
        - Two SRIO interfaces. Each supports up to 4 lanes and
          a total of up to 8 lanes
        - Up to 8-lanes Common Public Radio Interface (CPRI) controller
          for glue-less antenna connection
        - Two 10-Gbit Ethernet controllers (10GEC)
        - Six 1G/2.5-Gbit Ethernet controllers for network communications
        - PCI Express controller
        - Debug (Aurora)
    - Various system peripherals

B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500),
fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies.

Key differences between B4860 and B4420:
B4420 has:
    - Fewer e6500 cores:
        1 cluster with 2 e6500 cores
    - Fewer SC3900 cores/clusters:
        1 cluster with 2 SC3900 cores per cluster
    - Single DDRC
    - 2X 4 lane serdes
    - 3 SGMII interfaces
    - no sRIO
    - no 10G

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
 arch/powerpc/platforms/85xx/Makefile |    1 +
 arch/powerpc/platforms/85xx/b4_qds.c |  102 ++++++++++++++++++++++++++++++++++
 3 files changed, 119 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c

diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 31dc066..7bbd522 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -262,6 +262,22 @@ config SGY_CTS1000
 
 endif # PPC32
 
+config B4_QDS
+	bool "Freescale B4 QDS"
+	select DEFAULT_UIMAGE
+	select E500
+	select PPC_E500MC
+	select PHYS_64BIT
+	select SWIOTLB
+	select MPC8xxx_GPIO
+	select HAS_RAPIDIO
+	select PPC_EPAPR_HV_PIC
+	help
+	  This option enables support for the B4 QDS board
+	  The B4 application development system B4 QDS is a complete
+	  debugging environment intended for engineers developing
+	  applications for the B4.
+
 config P5020_DS
 	bool "Freescale P5020 DS"
 	select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 712e233..a12ae2d 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o
 obj-y += common.o
 
 obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
+obj-$(CONFIG_B4_QDS)   += b4_qds.o corenet_ds.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
new file mode 100644
index 0000000..0c6702f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/b4_qds.c
@@ -0,0 +1,102 @@
+/*
+ * B4 QDS Setup
+ * Should apply for QDS platform of B4860 and it's personalities.
+ * viz B4860/B4420/B4220QDS
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init b4_qds_probe(void)
+{
+	unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+	extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
+		(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
+			(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
+		return 1;
+
+	/* Check if we're running under the Freescale hypervisor */
+	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
+		(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
+			(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
+		ppc_md.init_IRQ = ehv_pic_init;
+		ppc_md.get_irq = ehv_pic_get_irq;
+		ppc_md.restart = fsl_hv_restart;
+		ppc_md.power_off = fsl_hv_halt;
+		ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+		/*
+		 * Disable the timebase sync operations because we can't write
+		 * to the timebase registers under the hypervisor.
+		  */
+		smp_85xx_ops.give_timebase = NULL;
+		smp_85xx_ops.take_timebase = NULL;
+#endif
+		return 1;
+	}
+
+	return 0;
+}
+
+define_machine(b4_qds) {
+	.name			= "B4 QDS",
+	.probe			= b4_qds_probe,
+	.setup_arch		= corenet_ds_setup_arch,
+	.init_IRQ		= corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+	.get_irq		= mpic_get_irq,
+#else
+	.get_irq		= mpic_get_coreint_irq,
+#endif
+	.restart		= fsl_rstcr_restart,
+	.calibrate_decr		= generic_calibrate_decr,
+	.progress		= udbg_progress,
+#ifdef CONFIG_PPC64
+	.power_save		= book3e_idle,
+#else
+	.power_save		= e500_idle,
+#endif
+};
+
+machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
+#endif
-- 
1.7.6.GIT

[PATCH 6/6] powerpc/85xx: Update corenet64_smp_defconfig for B4_QDS

[Shaveta Leekha]

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/configs/corenet64_smp_defconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 36a5c41..abf21ea 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -21,6 +21,7 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
+CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
 CONFIG_T4240_QDS=y
-- 
1.7.6.GIT

Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Timur Tabi]

On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha <shaveta@freescale.com> wrote:


> +       iommu@20000 {
> +               compatible = "fsl,pamu-v1.0", "fsl,pamu";
> +               reg = <0x20000 0x4000>;
> +               interrupts = <
> +                       24 2 0 0
> +                       16 2 1 1>;
> +       };

You need to add the PAMU topology.

-- 
Timur Tabi
Linux kernel developer at Freescale

Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  184 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   80 ++++++++++++
> 2 files changed, 264 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

Commit description should convey what hw isn't yet covered as well.

DPAA, DSPs, etc.

- k

>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..2db68b2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,184 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0x0 0xff>;
> +	interrupts =3D <20 2 0 0>;
> +	pcie@0 {
> +		#interrupt-cells =3D <1>;
> +		#size-cells =3D <2>;
> +		#address-cells =3D <3>;
> +		device_type =3D "pci";
> +		interrupts =3D <20 2 0 0>;
> +		interrupt-map-mask =3D <0xf800 0 0 7>;
> +		interrupt-map =3D <
> +			/* IDSEL 0x0 */
> +			0000 0 0 1 &mpic 40 1 0 0
> +			0000 0 0 2 &mpic 1 1 0 0
> +			0000 0 0 3 &mpic 2 1 0 0
> +			0000 0 0 4 &mpic 3 1 0 0
> +			>;
> +	};
> +};
> +
> +&rio {
> +	compatible =3D "fsl,srio";
> +	interrupts =3D <16 2 1 11>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	ranges;
> +
> +	port1 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <1>;
> +	};
> +
> +	port2 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <2>;
> +	};
> +};
> +
> +&soc {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	device_type =3D "soc";
> +	compatible =3D "simple-bus";
> +
> +	soc-sram-error {
> +		compatible =3D "fsl,soc-sram-error";
> +		interrupts =3D <16 2 1 2>;
> +	};
> +
> +	corenet-law@0 {
> +		compatible =3D "fsl,corenet-law";
> +		reg =3D <0x0 0x1000>;
> +		fsl,num-laws =3D <32>;
> +	};
> +
> +	ddr1: memory-controller@8000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> +		reg =3D <0x8000 0x1000>;
> +		interrupts =3D <16 2 1 8>;
> +	};
> +
> +	ddr2: memory-controller@9000 {
> +		compatible =3D =
"fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
> +		reg =3D <0x9000 0x1000>;
> +		interrupts =3D <16 2 1 9>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,p5020-l3-cache-controller", =
"fsl,p4080-l3-cache-controller", "cache";
> +		reg =3D <0x10000 0x1000
> +		       0x11000 0x1000>;
> +		interrupts =3D <16 2 1 4
> +			      16 2 1 5>;
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,corenet-cf";
> +		reg =3D <0x18000 0x1000>;
> +		interrupts =3D <16 2 1 0>;
> +		fsl,ccf-num-csdids =3D <32>;
> +		fsl,ccf-num-snoopids =3D <32>;
> +	};
> +
> +	iommu@20000 {
> +		compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> +		reg =3D <0x20000 0x4000>;
> +		interrupts =3D <
> +			24 2 0 0
> +			16 2 1 1>;
> +	};
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4860-device-config";
> +		reg =3D <0xe0000 0xe00>;
> +		fsl,has-rstcr;
> +		fsl,liodn-bits =3D <12>;
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4860-clockgen", =
"fsl,qoriq-clockgen-2";
> +		reg =3D <0xe1000 0x1000>;
> +	};
> +
> +	rcpm: global-utilities@e2000 {
> +		compatible =3D "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2";
> +		reg =3D <0xe2000 0x1000>;
> +	};
> +
> +/include/ "qoriq-dma-0.dtsi"
> +/include/ "qoriq-dma-1.dtsi"
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> +	usb0: usb@210000 {
> +		compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> +	};
> +
> +/include/ "qoriq-espi-0.dtsi"
> +	spi@110000 {
> +		fsl,espi-num-chipselects =3D <4>;
> +	};
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> +	sdhc@114000 {
> +		sdhci,auto-cmd12;
> +	};
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +
> +	L2: l2-cache-controller@c20000 {
> +		next-level-cache =3D <&cpc>;
> +	};
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> new file mode 100644
> index 0000000..33bc600
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -0,0 +1,80 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (pre include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +/ {
> +	compatible =3D "fsl,B4860";
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	interrupt-parent =3D <&mpic>;
> +
> +	aliases {
> +		ccsr =3D &soc;
> +
> +		serial0 =3D &serial0;
> +		serial1 =3D &serial1;
> +		serial2 =3D &serial2;
> +		serial3 =3D &serial3;
> +		pci0 =3D &pci0;
> +		dma0 =3D &dma0;
> +		dma1 =3D &dma1;
> +		sdhc =3D &sdhc;
> +	};
> +
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		PowerPC,e6500@0 {
> +			device_type =3D "cpu";
> +			reg =3D <0 1>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		PowerPC,e6500@1 {
> +			device_type =3D "cpu";
> +			reg =3D <2 3>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		PowerPC,e6500@2 {
> +			device_type =3D "cpu";
> +			reg =3D <4 5>;
> +			next-level-cache =3D <&L2>;
> +		};
> +		PowerPC,e6500@3 {
> +			device_type =3D "cpu";
> +			reg =3D <6 7>;
> +			next-level-cache =3D <&L2>;
> +		};
> +	};
> +};
> --=20
> 1.7.6.GIT
>=20

Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> - Add support for B4 board's personalities in board file
>  b4_qds.c, It is common for B4 personalities B4860 and B4420QDS
> - Add B4QDS support in Kconfig and Makefile

Code also references a B4220, what about it?

>=20
> B4860QDS is a high-performance computing evaluation, development and
> test platform supporting the B4860 QorIQ Power Architecture processor,
> with following major features:
>=20
>    - Four dual-threaded e6500 Power Architecture processors
>      organized in one cluster-each core runs up to 1.8 GHz
>    - Two DDR3/3L controllers for high-speed memory interface each
>      runs at up to 1866.67 MHz
>    - CoreNet fabric that fully supports coherency using MESI protocol
>      between the e6500 cores, SC3900 FVP cores, memories and
>      external interfaces.
>    - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC =
5.3 and RMAN
>    - Large internal cache memory with snooping and stashing =
capabilities
>    - Sixteen 10-GHz SerDes lanes that serve:
>        - Two SRIO interfaces. Each supports up to 4 lanes and
>          a total of up to 8 lanes
>        - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>          for glue-less antenna connection
>        - Two 10-Gbit Ethernet controllers (10GEC)
>        - Six 1G/2.5-Gbit Ethernet controllers for network =
communications
>        - PCI Express controller
>        - Debug (Aurora)
>    - Various system peripherals
>=20
> B4420 is a reduced personality of B4860 with fewer core/clusters(both =
SC3900 and e6500),
> fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and =
reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
>    - Fewer e6500 cores:
>        1 cluster with 2 e6500 cores
>    - Fewer SC3900 cores/clusters:
>        1 cluster with 2 SC3900 cores per cluster
>    - Single DDRC
>    - 2X 4 lane serdes
>    - 3 SGMII interfaces
>    - no sRIO
>    - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
> arch/powerpc/platforms/85xx/Makefile |    1 +
> arch/powerpc/platforms/85xx/b4_qds.c |  102 =
++++++++++++++++++++++++++++++++++
> 3 files changed, 119 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
>=20
> diff --git a/arch/powerpc/platforms/85xx/Kconfig =
b/arch/powerpc/platforms/85xx/Kconfig
> index 31dc066..7bbd522 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -262,6 +262,22 @@ config SGY_CTS1000
>=20
> endif # PPC32
>=20
> +config B4_QDS
> +	bool "Freescale B4 QDS"
> +	select DEFAULT_UIMAGE
> +	select E500
> +	select PPC_E500MC
> +	select PHYS_64BIT
> +	select SWIOTLB
> +	select MPC8xxx_GPIO

should be:
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB

> +	select HAS_RAPIDIO
> +	select PPC_EPAPR_HV_PIC
> +	help
> +	  This option enables support for the B4 QDS board
> +	  The B4 application development system B4 QDS is a complete
> +	  debugging environment intended for engineers developing
> +	  applications for the B4.
> +

Should be in the if PPC64 section with T4240 QDS support

> config P5020_DS
> 	bool "Freescale P5020 DS"
> 	select DEFAULT_UIMAGE
> diff --git a/arch/powerpc/platforms/85xx/Makefile =
b/arch/powerpc/platforms/85xx/Makefile
> index 712e233..a12ae2d 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) +=3D smp.o
> obj-y +=3D common.o
>=20
> obj-$(CONFIG_BSC9131_RDB) +=3D bsc913x_rdb.o
> +obj-$(CONFIG_B4_QDS)   +=3D b4_qds.o corenet_ds.o
> obj-$(CONFIG_MPC8540_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC8560_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) +=3D mpc85xx_cds.o
> diff --git a/arch/powerpc/platforms/85xx/b4_qds.c =
b/arch/powerpc/platforms/85xx/b4_qds.c
> new file mode 100644
> index 0000000..0c6702f
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/b4_qds.c
> @@ -0,0 +1,102 @@
> +/*
> + * B4 QDS Setup
> + * Should apply for QDS platform of B4860 and it's personalities.
> + * viz B4860/B4420/B4220QDS
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute  it and/or =
modify it
> + * under  the terms of  the GNU General  Public License as published =
by the
> + * Free Software Foundation;  either version 2 of the  License, or =
(at your
> + * option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/phy.h>
> +
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <linux/of_platform.h>
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +#include <asm/ehv_pic.h>
> +
> +#include "corenet_ds.h"
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init b4_qds_probe(void)
> +{
> +	unsigned long root =3D of_get_flat_dt_root();
> +#ifdef CONFIG_SMP
> +	extern struct smp_ops_t smp_85xx_ops;
> +#endif
> +
> +	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
> +		(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
> +			(of_flat_dt_is_compatible(root, =
"fsl,B4220QDS")))
> +		return 1;
> +
> +	/* Check if we're running under the Freescale hypervisor */
> +	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
> +		(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
> +			(of_flat_dt_is_compatible(root, =
"fsl,B4220QDS-hv"))) {
> +		ppc_md.init_IRQ =3D ehv_pic_init;
> +		ppc_md.get_irq =3D ehv_pic_get_irq;
> +		ppc_md.restart =3D fsl_hv_restart;
> +		ppc_md.power_off =3D fsl_hv_halt;
> +		ppc_md.halt =3D fsl_hv_halt;
> +#ifdef CONFIG_SMP
> +		/*
> +		 * Disable the timebase sync operations because we can't =
write
> +		 * to the timebase registers under the hypervisor.
> +		  */
> +		smp_85xx_ops.give_timebase =3D NULL;
> +		smp_85xx_ops.take_timebase =3D NULL;
> +#endif
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +define_machine(b4_qds) {
> +	.name			=3D "B4 QDS",
> +	.probe			=3D b4_qds_probe,
> +	.setup_arch		=3D corenet_ds_setup_arch,
> +	.init_IRQ		=3D corenet_ds_pic_init,
> +#ifdef CONFIG_PCI
> +	.pcibios_fixup_bus	=3D fsl_pcibios_fixup_bus,
> +#endif
> +/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
> +#ifdef CONFIG_PPC64
> +	.get_irq		=3D mpic_get_irq,
> +#else
> +	.get_irq		=3D mpic_get_coreint_irq,
> +#endif
> +	.restart		=3D fsl_rstcr_restart,
> +	.calibrate_decr		=3D generic_calibrate_decr,
> +	.progress		=3D udbg_progress,
> +#ifdef CONFIG_PPC64
> +	.power_save		=3D book3e_idle,
> +#else
> +	.power_save		=3D e500_idle,
> +#endif
> +};
> +
> +machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
> +
> +#ifdef CONFIG_SWIOTLB
> +machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
> +#endif
> --=20
> 1.7.6.GIT
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/b4860qds.dts |  178 =
++++++++++++++++++++++++++++++++++++
> 1 files changed, 178 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/b4860qds.dts
>=20
> diff --git a/arch/powerpc/boot/dts/b4860qds.dts =
b/arch/powerpc/boot/dts/b4860qds.dts
> new file mode 100644
> index 0000000..ae6ac05
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/b4860qds.dts
> @@ -0,0 +1,178 @@
> +/*
> + * B4860DS Device Tree Source
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "fsl/b4860si-pre.dtsi"
> +
> +/ {
> +	model =3D "fsl,B4860QDS";
> +	compatible =3D "fsl,B4860QDS";
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	interrupt-parent =3D <&mpic>;
> +
> +	ifc: localbus@ffe124000 {
> +		reg =3D <0xf 0xfe124000 0 0x2000>;
> +		ranges =3D <0 0 0xf 0xe8000000 0x08000000
> +			  2 0 0xf 0xff800000 0x00010000
> +			  3 0 0xf 0xffdf0000 0x00008000>;
> +
> +		nor@0,0 {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			compatible =3D "cfi-flash";
> +			reg =3D <0x0 0x0 0x8000000>;
> +			bank-width =3D <2>;
> +			device-width =3D <1>;
> +		};
> +
> +		nand@2,0 {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			compatible =3D "fsl,ifc-nand";
> +			reg =3D <0x2 0x0 0x10000>;
> +
> +			partition@0 {
> +				/* This location must not be altered  */
> +				/* 1MB for u-boot Bootloader Image */
> +				reg =3D <0x0 0x00100000>;
> +				label =3D "NAND U-Boot Image";
> +				read-only;
> +			};
> +
> +			partition@100000 {
> +				/* 1MB for DTB Image */
> +				reg =3D <0x00100000 0x00100000>;
> +				label =3D "NAND DTB Image";
> +			};
> +
> +			partition@200000 {
> +				/* 10MB for Linux Kernel Image */
> +				reg =3D <0x00200000 0x00A00000>;
> +				label =3D "NAND Linux Kernel Image";
> +			};
> +
> +			partition@c00000 {
> +				/* 500MB for Root file System Image */
> +				reg =3D <0x00c00000 0x1F400000>;
> +				label =3D "NAND RFS Image";
> +			};
> +		};
> +
> +		board-control@3,0 {
> +			compatible =3D "fsl,b4860qds-fpga", =
"fsl,fpga-qixis";
> +			reg =3D <3 0 0x300>;
> +		};
> +	};
> +

dscr nodes are missing and should be included


> +	memory {
> +		device_type =3D "memory";
> +	};
> +
> +	soc: soc@ffe000000 {
> +		ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
> +		reg =3D <0xf 0xfe000000 0 0x00001000>;
> +		spi@110000 {
> +			flash@0 {
> +				#address-cells =3D <1>;
> +				#size-cells =3D <1>;
> +				compatible =3D "sst,sst25wf040";
> +				reg =3D <0>;
> +				spi-max-frequency =3D <40000000>; /* =
input clock */
> +			};
> +		};
> +
> +		sdhc@114000 {
> +			status =3D "disabled";
> +		};
> +
> +		i2c@118000 {
> +			eeprom@50 {
> +				compatible =3D "at24,24c64";
> +				reg =3D <0x50>;
> +			};
> +			eeprom@51 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x51>;
> +			};
> +			eeprom@53 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x53>;
> +			};
> +			eeprom@57 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x57>;
> +			};
> +			rtc@68 {
> +				compatible =3D "dallas,ds3232";
> +				reg =3D <0x68>;
> +				interrupts =3D <0x1 0x1 0 0>;

there is no IRQ for RTC on the board.

> +			};
> +		};
> +
> +		usb@210000 {
> +			dr_mode =3D "host";
> +			phy_type =3D "ulpi";
> +		};
> +
> +	};
> +
> +	pci0: pcie@ffe200000 {
> +		reg =3D <0xf 0xfe200000 0 0x10000>;
> +		ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 =
0x20000000
> +			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 =
0x00010000>;
> +		pcie@0 {
> +			ranges =3D <0x02000000 0 0xe0000000
> +				  0x02000000 0 0xe0000000
> +				  0 0x20000000
> +
> +				  0x01000000 0 0x00000000
> +				  0x01000000 0 0x00000000
> +				  0 0x00010000>;
> +		};
> +	};
> +
> +	rio: rapidio@ffe0c0000 {
> +		reg =3D <0xf 0xfe0c0000 0 0x11000>;
> +
> +		port1 {
> +			ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
> +		};
> +		port2 {
> +			ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
> +		};
> +	};
> +
> +};
> +
> +/include/ "fsl/b4860si-post.dtsi"
> --=20
> 1.7.6.GIT
>=20

Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  184 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   80 ++++++++++++
> 2 files changed, 264 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

* SEC node is missing
* DCSR nodes are missing.

- k

>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi =
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..2db68b2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,184 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + *     * Redistributions of source code must retain the above =
copyright
> + *       notice, this list of conditions and the following =
disclaimer.
> + *     * Redistributions in binary form must reproduce the above =
copyright
> + *       notice, this list of conditions and the following disclaimer =
in the
> + *       documentation and/or other materials provided with the =
distribution.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote =
products
> + *       derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0x0 0xff>;
> +	interrupts =3D <20 2 0 0>;
> +	pcie@0 {
> +		#interrupt-cells =3D <1>;
> +		#size-cells =3D <2>;
> +		#address-cells =3D <3>;
> +		device_type =3D "pci";
> +		interrupts =3D <20 2 0 0>;
> +		interrupt-map-mask =3D <0xf800 0 0 7>;
> +		interrupt-map =3D <
> +			/* IDSEL 0x0 */
> +			0000 0 0 1 &mpic 40 1 0 0
> +			0000 0 0 2 &mpic 1 1 0 0
> +			0000 0 0 3 &mpic 2 1 0 0
> +			0000 0 0 4 &mpic 3 1 0 0
> +			>;
> +	};
> +};
> +
> +&rio {
> +	compatible =3D "fsl,srio";
> +	interrupts =3D <16 2 1 11>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	ranges;
> +
> +	port1 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <1>;
> +	};
> +
> +	port2 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <2>;
> +	};
> +};
> +
> +&soc {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	device_type =3D "soc";
> +	compatible =3D "simple-bus";
> +
> +	soc-sram-error {
> +		compatible =3D "fsl,soc-sram-error";
> +		interrupts =3D <16 2 1 2>;
> +	};
> +
> +	corenet-law@0 {
> +		compatible =3D "fsl,corenet-law";
> +		reg =3D <0x0 0x1000>;
> +		fsl,num-laws =3D <32>;
> +	};
> +
> +	ddr1: memory-controller@8000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", =
"fsl,qoriq-memory-controller";
> +		reg =3D <0x8000 0x1000>;
> +		interrupts =3D <16 2 1 8>;
> +	};
> +
> +	ddr2: memory-controller@9000 {
> +		compatible =3D =
"fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
> +		reg =3D <0x9000 0x1000>;
> +		interrupts =3D <16 2 1 9>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,p5020-l3-cache-controller", =
"fsl,p4080-l3-cache-controller", "cache";
> +		reg =3D <0x10000 0x1000
> +		       0x11000 0x1000>;
> +		interrupts =3D <16 2 1 4
> +			      16 2 1 5>;
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,corenet-cf";
> +		reg =3D <0x18000 0x1000>;
> +		interrupts =3D <16 2 1 0>;
> +		fsl,ccf-num-csdids =3D <32>;
> +		fsl,ccf-num-snoopids =3D <32>;
> +	};
> +
> +	iommu@20000 {
> +		compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> +		reg =3D <0x20000 0x4000>;
> +		interrupts =3D <
> +			24 2 0 0
> +			16 2 1 1>;
> +	};
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4860-device-config";
> +		reg =3D <0xe0000 0xe00>;
> +		fsl,has-rstcr;
> +		fsl,liodn-bits =3D <12>;
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4860-clockgen", =
"fsl,qoriq-clockgen-2";
> +		reg =3D <0xe1000 0x1000>;
> +	};
> +
> +	rcpm: global-utilities@e2000 {
> +		compatible =3D "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2";
> +		reg =3D <0xe2000 0x1000>;
> +	};
> +
> +/include/ "qoriq-dma-0.dtsi"
> +/include/ "qoriq-dma-1.dtsi"
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> +	usb0: usb@210000 {
> +		compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> +	};
> +
> +/include/ "qoriq-espi-0.dtsi"
> +	spi@110000 {
> +		fsl,espi-num-chipselects =3D <4>;
> +	};
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> +	sdhc@114000 {
> +		sdhci,auto-cmd12;
> +	};
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +
> +	L2: l2-cache-controller@c20000 {
> +		next-level-cache =3D <&cpc>;

should have compatible & reg nodes

> +	};
> +};

[ snip ]

- k=

Re: [PATCH 3/6] powerpc/fsl-booke: Add initial silicon device tree files for B4420QDS

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi |  151 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi  |   70 ++++++++++++
> 2 files changed, 221 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

Similar comments to B4860 dts files.

- k=

Re: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree

[Kumar Gala]

On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/boot/dts/b4420qds.dts |  168 =
++++++++++++++++++++++++++++++++++++
> 1 files changed, 168 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/b4420qds.dts

If B4420 and B4860 qds are same board, refactor this into a b4qds.dtsi =
file for common board features like NOR, NAND, SPI, SDHC, etc.

- k=

RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, March 15, 2013 9:28 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support


On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> - Add support for B4 board's personalities in board file  b4_qds.c, It=20
> is common for B4 personalities B4860 and B4420QDS
> - Add B4QDS support in Kconfig and Makefile

Code also references a B4220, what about it?
[SL] I have added the basic support for it in board file as it's one of the=
 personality of
B4, missed it in description. But device trees for this has not been create=
d and tested.
So what do you suggest here:
Should I add it here in B4 board support or should I remove its references =
altogether?

>=20
> B4860QDS is a high-performance computing evaluation, development and=20
> test platform supporting the B4860 QorIQ Power Architecture processor,=20
> with following major features:
>=20
>    - Four dual-threaded e6500 Power Architecture processors
>      organized in one cluster-each core runs up to 1.8 GHz
>    - Two DDR3/3L controllers for high-speed memory interface each
>      runs at up to 1866.67 MHz
>    - CoreNet fabric that fully supports coherency using MESI protocol
>      between the e6500 cores, SC3900 FVP cores, memories and
>      external interfaces.
>    - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3=
 and RMAN
>    - Large internal cache memory with snooping and stashing capabilities
>    - Sixteen 10-GHz SerDes lanes that serve:
>        - Two SRIO interfaces. Each supports up to 4 lanes and
>          a total of up to 8 lanes
>        - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>          for glue-less antenna connection
>        - Two 10-Gbit Ethernet controllers (10GEC)
>        - Six 1G/2.5-Gbit Ethernet controllers for network communications
>        - PCI Express controller
>        - Debug (Aurora)
>    - Various system peripherals
>=20
> B4420 is a reduced personality of B4860 with fewer core/clusters(both=20
> SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII=
 interfaces and reduced target frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
>    - Fewer e6500 cores:
>        1 cluster with 2 e6500 cores
>    - Fewer SC3900 cores/clusters:
>        1 cluster with 2 SC3900 cores per cluster
>    - Single DDRC
>    - 2X 4 lane serdes
>    - 3 SGMII interfaces
>    - no sRIO
>    - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
> arch/powerpc/platforms/85xx/Makefile |    1 +
> arch/powerpc/platforms/85xx/b4_qds.c |  102=20
> ++++++++++++++++++++++++++++++++++
> 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/platforms/85xx/b4_qds.c
>=20
> diff --git a/arch/powerpc/platforms/85xx/Kconfig=20
> b/arch/powerpc/platforms/85xx/Kconfig
> index 31dc066..7bbd522 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -262,6 +262,22 @@ config SGY_CTS1000
>=20
> endif # PPC32
>=20
> +config B4_QDS
> +	bool "Freescale B4 QDS"
> +	select DEFAULT_UIMAGE
> +	select E500
> +	select PPC_E500MC
> +	select PHYS_64BIT
> +	select SWIOTLB
> +	select MPC8xxx_GPIO

should be:
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB

[SL] will change it.
=20
> +	select HAS_RAPIDIO
> +	select PPC_EPAPR_HV_PIC
> +	help
> +	  This option enables support for the B4 QDS board
> +	  The B4 application development system B4 QDS is a complete
> +	  debugging environment intended for engineers developing
> +	  applications for the B4.
> +

Should be in the if PPC64 section with T4240 QDS support
[SL] ok=20

> config P5020_DS
> 	bool "Freescale P5020 DS"
> 	select DEFAULT_UIMAGE
> diff --git a/arch/powerpc/platforms/85xx/Makefile=20
> b/arch/powerpc/platforms/85xx/Makefile
> index 712e233..a12ae2d 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) +=3D smp.o obj-y +=3D common.o
>=20
> obj-$(CONFIG_BSC9131_RDB) +=3D bsc913x_rdb.o
> +obj-$(CONFIG_B4_QDS)   +=3D b4_qds.o corenet_ds.o
> obj-$(CONFIG_MPC8540_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC8560_ADS) +=3D mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) +=3D mpc85xx_cds.o diff --git=20
> a/arch/powerpc/platforms/85xx/b4_qds.c=20
> b/arch/powerpc/platforms/85xx/b4_qds.c
> new file mode 100644
> index 0000000..0c6702f
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/b4_qds.c
> @@ -0,0 +1,102 @@
> +/*
> + * B4 QDS Setup
> + * Should apply for QDS platform of B4860 and it's personalities.
> + * viz B4860/B4420/B4220QDS
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute  it and/or=20
> +modify it
> + * under  the terms of  the GNU General  Public License as published=20
> +by the
> + * Free Software Foundation;  either version 2 of the  License, or=20
> +(at your
> + * option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/phy.h>
> +
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <linux/of_platform.h>
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +#include <asm/ehv_pic.h>
> +
> +#include "corenet_ds.h"
> +
> +/*
> + * Called very early, device-tree isn't unflattened  */ static int=20
> +__init b4_qds_probe(void) {
> +	unsigned long root =3D of_get_flat_dt_root(); #ifdef CONFIG_SMP
> +	extern struct smp_ops_t smp_85xx_ops; #endif
> +
> +	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
> +		(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
> +			(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
> +		return 1;
> +
> +	/* Check if we're running under the Freescale hypervisor */
> +	if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
> +		(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
> +			(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
> +		ppc_md.init_IRQ =3D ehv_pic_init;
> +		ppc_md.get_irq =3D ehv_pic_get_irq;
> +		ppc_md.restart =3D fsl_hv_restart;
> +		ppc_md.power_off =3D fsl_hv_halt;
> +		ppc_md.halt =3D fsl_hv_halt;
> +#ifdef CONFIG_SMP
> +		/*
> +		 * Disable the timebase sync operations because we can't write
> +		 * to the timebase registers under the hypervisor.
> +		  */
> +		smp_85xx_ops.give_timebase =3D NULL;
> +		smp_85xx_ops.take_timebase =3D NULL;
> +#endif
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
> +define_machine(b4_qds) {
> +	.name			=3D "B4 QDS",
> +	.probe			=3D b4_qds_probe,
> +	.setup_arch		=3D corenet_ds_setup_arch,
> +	.init_IRQ		=3D corenet_ds_pic_init,
> +#ifdef CONFIG_PCI
> +	.pcibios_fixup_bus	=3D fsl_pcibios_fixup_bus,
> +#endif
> +/* coreint doesn't play nice with lazy EE, use legacy mpic for now */=20
> +#ifdef CONFIG_PPC64
> +	.get_irq		=3D mpic_get_irq,
> +#else
> +	.get_irq		=3D mpic_get_coreint_irq,
> +#endif
> +	.restart		=3D fsl_rstcr_restart,
> +	.calibrate_decr		=3D generic_calibrate_decr,
> +	.progress		=3D udbg_progress,
> +#ifdef CONFIG_PPC64
> +	.power_save		=3D book3e_idle,
> +#else
> +	.power_save		=3D e500_idle,
> +#endif
> +};
> +
> +machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
> +
> +#ifdef CONFIG_SWIOTLB
> +machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier); #endif
> --
> 1.7.6.GIT
>=20
>=20

Regards,
Shaveta

=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 1:57 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEM=
ING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board devi=
ce tree


On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/b4860qds.dts |  178=20
> ++++++++++++++++++++++++++++++++++++
> 1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/b4860qds.dts
>=20
> diff --git a/arch/powerpc/boot/dts/b4860qds.dts=20
> b/arch/powerpc/boot/dts/b4860qds.dts
> new file mode 100644
> index 0000000..ae6ac05
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/b4860qds.dts
> @@ -0,0 +1,178 @@
> +/*
> + * B4860DS Device Tree Source
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "fsl/b4860si-pre.dtsi"
> +
> +/ {
> +	model =3D "fsl,B4860QDS";
> +	compatible =3D "fsl,B4860QDS";
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	interrupt-parent =3D <&mpic>;
> +
> +	ifc: localbus@ffe124000 {
> +		reg =3D <0xf 0xfe124000 0 0x2000>;
> +		ranges =3D <0 0 0xf 0xe8000000 0x08000000
> +			  2 0 0xf 0xff800000 0x00010000
> +			  3 0 0xf 0xffdf0000 0x00008000>;
> +
> +		nor@0,0 {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			compatible =3D "cfi-flash";
> +			reg =3D <0x0 0x0 0x8000000>;
> +			bank-width =3D <2>;
> +			device-width =3D <1>;
> +		};
> +
> +		nand@2,0 {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			compatible =3D "fsl,ifc-nand";
> +			reg =3D <0x2 0x0 0x10000>;
> +
> +			partition@0 {
> +				/* This location must not be altered  */
> +				/* 1MB for u-boot Bootloader Image */
> +				reg =3D <0x0 0x00100000>;
> +				label =3D "NAND U-Boot Image";
> +				read-only;
> +			};
> +
> +			partition@100000 {
> +				/* 1MB for DTB Image */
> +				reg =3D <0x00100000 0x00100000>;
> +				label =3D "NAND DTB Image";
> +			};
> +
> +			partition@200000 {
> +				/* 10MB for Linux Kernel Image */
> +				reg =3D <0x00200000 0x00A00000>;
> +				label =3D "NAND Linux Kernel Image";
> +			};
> +
> +			partition@c00000 {
> +				/* 500MB for Root file System Image */
> +				reg =3D <0x00c00000 0x1F400000>;
> +				label =3D "NAND RFS Image";
> +			};
> +		};
> +
> +		board-control@3,0 {
> +			compatible =3D "fsl,b4860qds-fpga", "fsl,fpga-qixis";
> +			reg =3D <3 0 0x300>;
> +		};
> +	};
> +

dscr nodes are missing and should be included
[SL] I don't have much idea about dcsr nodes structure and their respective=
 testing, also couldn't find then in T4 device tree files. I have added ini=
tial device trees. Dcsr may be added later as updation. What do you say? =20


> +	memory {
> +		device_type =3D "memory";
> +	};
> +
> +	soc: soc@ffe000000 {
> +		ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
> +		reg =3D <0xf 0xfe000000 0 0x00001000>;
> +		spi@110000 {
> +			flash@0 {
> +				#address-cells =3D <1>;
> +				#size-cells =3D <1>;
> +				compatible =3D "sst,sst25wf040";
> +				reg =3D <0>;
> +				spi-max-frequency =3D <40000000>; /* input clock */
> +			};
> +		};
> +
> +		sdhc@114000 {
> +			status =3D "disabled";
> +		};
> +
> +		i2c@118000 {
> +			eeprom@50 {
> +				compatible =3D "at24,24c64";
> +				reg =3D <0x50>;
> +			};
> +			eeprom@51 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x51>;
> +			};
> +			eeprom@53 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x53>;
> +			};
> +			eeprom@57 {
> +				compatible =3D "at24,24c256";
> +				reg =3D <0x57>;
> +			};
> +			rtc@68 {
> +				compatible =3D "dallas,ds3232";
> +				reg =3D <0x68>;
> +				interrupts =3D <0x1 0x1 0 0>;

there is no IRQ for RTC on the board.
[SL] will remove it.=20

> +			};
> +		};
> +
> +		usb@210000 {
> +			dr_mode =3D "host";
> +			phy_type =3D "ulpi";
> +		};
> +
> +	};
> +
> +	pci0: pcie@ffe200000 {
> +		reg =3D <0xf 0xfe200000 0 0x10000>;
> +		ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
> +			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
> +		pcie@0 {
> +			ranges =3D <0x02000000 0 0xe0000000
> +				  0x02000000 0 0xe0000000
> +				  0 0x20000000
> +
> +				  0x01000000 0 0x00000000
> +				  0x01000000 0 0x00000000
> +				  0 0x00010000>;
> +		};
> +	};
> +
> +	rio: rapidio@ffe0c0000 {
> +		reg =3D <0xf 0xfe0c0000 0 0x11000>;
> +
> +		port1 {
> +			ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
> +		};
> +		port2 {
> +			ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
> +		};
> +	};
> +
> +};
> +
> +/include/ "fsl/b4860si-post.dtsi"
> --
> 1.7.6.GIT
>=20


Regards,
Shaveta
=20

RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 2:00 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tan=
g Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramnee=
k-B31383; Fleming Andy-AFLEMING
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860QDS


On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi |  184 ++++++++++++++++++++++=
+++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi  |   80 ++++++++++++
> 2 files changed, 264 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

* SEC node is missing
* DCSR nodes are missing.

- k

[SL] will add sec node, same reply for dcsr.


>=20
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi=20
> b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> new file mode 100644
> index 0000000..2db68b2
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -0,0 +1,184 @@
> +/*
> + * B4860 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2012 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions ar=
e met:
> + *     * Redistributions of source code must retain the above copyright
> + *       notice, this list of conditions and the following disclaimer.
> + *     * Redistributions in binary form must reproduce the above copyrig=
ht
> + *       notice, this list of conditions and the following disclaimer in=
 the
> + *       documentation and/or other materials provided with the distribu=
tion.
> + *     * Neither the name of Freescale Semiconductor nor the
> + *       names of its contributors may be used to endorse or promote pro=
ducts
> + *       derived from this software without specific prior written permi=
ssion.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of=20
> +the
> + * GNU General Public License ("GPL") as published by the Free=20
> +Software
> + * Foundation, either version 2 of that License or (at your option)=20
> +any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND=20
> +ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
> +IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE=20
> +ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
> +FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL=20
> +DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=20
> +SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
> +CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,=20
> +OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
> +USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> +	#address-cells =3D <2>;
> +	#size-cells =3D <1>;
> +	compatible =3D "fsl,ifc", "simple-bus";
> +	interrupts =3D <25 2 0 0>;
> +};
> +
> +/* controller at 0x200000 */
> +&pci0 {
> +	compatible =3D "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
> +	device_type =3D "pci";
> +	#size-cells =3D <2>;
> +	#address-cells =3D <3>;
> +	bus-range =3D <0x0 0xff>;
> +	interrupts =3D <20 2 0 0>;
> +	pcie@0 {
> +		#interrupt-cells =3D <1>;
> +		#size-cells =3D <2>;
> +		#address-cells =3D <3>;
> +		device_type =3D "pci";
> +		interrupts =3D <20 2 0 0>;
> +		interrupt-map-mask =3D <0xf800 0 0 7>;
> +		interrupt-map =3D <
> +			/* IDSEL 0x0 */
> +			0000 0 0 1 &mpic 40 1 0 0
> +			0000 0 0 2 &mpic 1 1 0 0
> +			0000 0 0 3 &mpic 2 1 0 0
> +			0000 0 0 4 &mpic 3 1 0 0
> +			>;
> +	};
> +};
> +
> +&rio {
> +	compatible =3D "fsl,srio";
> +	interrupts =3D <16 2 1 11>;
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +	ranges;
> +
> +	port1 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <1>;
> +	};
> +
> +	port2 {
> +		#address-cells =3D <2>;
> +		#size-cells =3D <2>;
> +		cell-index =3D <2>;
> +	};
> +};
> +
> +&soc {
> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	device_type =3D "soc";
> +	compatible =3D "simple-bus";
> +
> +	soc-sram-error {
> +		compatible =3D "fsl,soc-sram-error";
> +		interrupts =3D <16 2 1 2>;
> +	};
> +
> +	corenet-law@0 {
> +		compatible =3D "fsl,corenet-law";
> +		reg =3D <0x0 0x1000>;
> +		fsl,num-laws =3D <32>;
> +	};
> +
> +	ddr1: memory-controller@8000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-c=
ontroller";
> +		reg =3D <0x8000 0x1000>;
> +		interrupts =3D <16 2 1 8>;
> +	};
> +
> +	ddr2: memory-controller@9000 {
> +		compatible =3D "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-co=
ntroller";
> +		reg =3D <0x9000 0x1000>;
> +		interrupts =3D <16 2 1 9>;
> +	};
> +
> +	cpc: l3-cache-controller@10000 {
> +		compatible =3D "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-co=
ntroller", "cache";
> +		reg =3D <0x10000 0x1000
> +		       0x11000 0x1000>;
> +		interrupts =3D <16 2 1 4
> +			      16 2 1 5>;
> +	};
> +
> +	corenet-cf@18000 {
> +		compatible =3D "fsl,corenet-cf";
> +		reg =3D <0x18000 0x1000>;
> +		interrupts =3D <16 2 1 0>;
> +		fsl,ccf-num-csdids =3D <32>;
> +		fsl,ccf-num-snoopids =3D <32>;
> +	};
> +
> +	iommu@20000 {
> +		compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> +		reg =3D <0x20000 0x4000>;
> +		interrupts =3D <
> +			24 2 0 0
> +			16 2 1 1>;
> +	};
> +
> +/include/ "qoriq-mpic.dtsi"
> +
> +	guts: global-utilities@e0000 {
> +		compatible =3D "fsl,b4860-device-config";
> +		reg =3D <0xe0000 0xe00>;
> +		fsl,has-rstcr;
> +		fsl,liodn-bits =3D <12>;
> +	};
> +
> +	clockgen: global-utilities@e1000 {
> +		compatible =3D "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
> +		reg =3D <0xe1000 0x1000>;
> +	};
> +
> +	rcpm: global-utilities@e2000 {
> +		compatible =3D "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2";
> +		reg =3D <0xe2000 0x1000>;
> +	};
> +
> +/include/ "qoriq-dma-0.dtsi"
> +/include/ "qoriq-dma-1.dtsi"
> +
> +/include/ "qonverge-usb2-dr-0.dtsi"
> +	usb0: usb@210000 {
> +		compatible =3D "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
> +	};
> +
> +/include/ "qoriq-espi-0.dtsi"
> +	spi@110000 {
> +		fsl,espi-num-chipselects =3D <4>;
> +	};
> +
> +/include/ "qoriq-esdhc-0.dtsi"
> +	sdhc@114000 {
> +		sdhci,auto-cmd12;
> +	};
> +/include/ "qoriq-i2c-0.dtsi"
> +/include/ "qoriq-i2c-1.dtsi"
> +/include/ "qoriq-duart-0.dtsi"
> +/include/ "qoriq-duart-1.dtsi"
> +
> +	L2: l2-cache-controller@c20000 {
> +		next-level-cache =3D <&cpc>;

should have compatible & reg nodes
[SL] agree. Will add=20

> +	};
> +};

[ snip ]

- k

Regards,
Shaveta

RE: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board device tree

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Saturday, March 16, 2013 2:02 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 4/6] powerpc/fsl-booke: Add initial B4420QDS board devi=
ce tree


On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:

> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/boot/dts/b4420qds.dts |  168=20
> ++++++++++++++++++++++++++++++++++++
> 1 files changed, 168 insertions(+), 0 deletions(-) create mode 100644=20
> arch/powerpc/boot/dts/b4420qds.dts

If B4420 and B4860 qds are same board, refactor this into a b4qds.dtsi file=
 for common board features like NOR, NAND, SPI, SDHC, etc.

[SL] will work on refactoring and send new set of patches soon. Thanks for =
the feedback.

Regards,
Shaveta
=20
- k

RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Leekha Shaveta-B20052]

-----Original Message-----
From: Timur Tabi [mailto:timur@tabi.org]=20
Sent: Friday, March 15, 2013 6:38 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B3193=
9; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Set=
hi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860QDS

On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha <shaveta@freescale.com> wro=
te:


> +       iommu@20000 {
> +               compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
> +               reg =3D <0x20000 0x4000>;
> +               interrupts =3D <
> +                       24 2 0 0
> +                       16 2 1 1>;
> +       };

You need to add the PAMU topology.
[SL] Thanks for reviewing the patches.
These patches are on similar lines as T4 initial support
In due course of time, we plan to add pamu topology and pamu related suppor=
t in various devices both for T4 and B4.
Kumar can you please suggest?

Regards,
Shaveta

--=20
Timur Tabi
Linux kernel developer at Freescale

Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Kumar Gala]

On Mar 18, 2013, at 1:28 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Friday, March 15, 2013 9:28 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
>=20
>> - Add support for B4 board's personalities in board file  b4_qds.c, =
It=20
>> is common for B4 personalities B4860 and B4420QDS
>> - Add B4QDS support in Kconfig and Makefile
>=20
> Code also references a B4220, what about it?
> [SL] I have added the basic support for it in board file as it's one =
of the personality of
> B4, missed it in description. But device trees for this has not been =
created and tested.
> So what do you suggest here:
> Should I add it here in B4 board support or should I remove its =
references altogether?

What's the difference between B4220 and B4420 or B4860?

- k

>=20
>>=20
>> B4860QDS is a high-performance computing evaluation, development and=20=

>> test platform supporting the B4860 QorIQ Power Architecture =
processor,=20
>> with following major features:
>>=20
>>   - Four dual-threaded e6500 Power Architecture processors
>>     organized in one cluster-each core runs up to 1.8 GHz
>>   - Two DDR3/3L controllers for high-speed memory interface each
>>     runs at up to 1866.67 MHz
>>   - CoreNet fabric that fully supports coherency using MESI protocol
>>     between the e6500 cores, SC3900 FVP cores, memories and
>>     external interfaces.
>>   - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC =
5.3 and RMAN
>>   - Large internal cache memory with snooping and stashing =
capabilities
>>   - Sixteen 10-GHz SerDes lanes that serve:
>>       - Two SRIO interfaces. Each supports up to 4 lanes and
>>         a total of up to 8 lanes
>>       - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>>         for glue-less antenna connection
>>       - Two 10-Gbit Ethernet controllers (10GEC)
>>       - Six 1G/2.5-Gbit Ethernet controllers for network =
communications
>>       - PCI Express controller
>>       - Debug (Aurora)
>>   - Various system peripherals
>>=20
>> B4420 is a reduced personality of B4860 with fewer core/clusters(both=20=

>> SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer =
SGMII interfaces and reduced target frequencies.
>>=20
>> Key differences between B4860 and B4420:
>> B4420 has:
>>   - Fewer e6500 cores:
>>       1 cluster with 2 e6500 cores
>>   - Fewer SC3900 cores/clusters:
>>       1 cluster with 2 SC3900 cores per cluster
>>   - Single DDRC
>>   - 2X 4 lane serdes
>>   - 3 SGMII interfaces
>>   - no sRIO
>>   - no 10G
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> ---
>> arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
>> arch/powerpc/platforms/85xx/Makefile |    1 +
>> arch/powerpc/platforms/85xx/b4_qds.c |  102=20
>> ++++++++++++++++++++++++++++++++++
>> 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644=20=

>> arch/powerpc/platforms/85xx/b4_qds.c

Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Kumar Gala]

On Mar 18, 2013, at 1:31 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Saturday, March 16, 2013 1:57 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming =
Andy-AFLEMING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
> Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board =
device tree
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> arch/powerpc/boot/dts/b4860qds.dts |  178=20
>> ++++++++++++++++++++++++++++++++++++
>> 1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644=20=

>> arch/powerpc/boot/dts/b4860qds.dts
>>=20
>> diff --git a/arch/powerpc/boot/dts/b4860qds.dts=20
>> b/arch/powerpc/boot/dts/b4860qds.dts
>> new file mode 100644
>> index 0000000..ae6ac05
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/b4860qds.dts
>> @@ -0,0 +1,178 @@
>> +/*
>> + * B4860DS Device Tree Source
>> + *
>> + * Copyright 2012 Freescale Semiconductor Inc.
>> + *
>> + * Redistribution and use in source and binary forms, with or =
without
>> + * modification, are permitted provided that the following =
conditions are met:
>> + *     * Redistributions of source code must retain the above =
copyright
>> + *       notice, this list of conditions and the following =
disclaimer.
>> + *     * Redistributions in binary form must reproduce the above =
copyright
>> + *       notice, this list of conditions and the following =
disclaimer in the
>> + *       documentation and/or other materials provided with the =
distribution.
>> + *     * Neither the name of Freescale Semiconductor nor the
>> + *       names of its contributors may be used to endorse or promote =
products
>> + *       derived from this software without specific prior written =
permission.
>> + *
>> + *
>> + * ALTERNATIVELY, this software may be distributed under the terms =
of=20
>> +the
>> + * GNU General Public License ("GPL") as published by the Free=20
>> +Software
>> + * Foundation, either version 2 of that License or (at your option)=20=

>> +any
>> + * later version.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' =
AND=20
>> +ANY
>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20=

>> +IMPLIED
>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR =
PURPOSE=20
>> +ARE
>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20=

>> +FOR ANY
>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR =
CONSEQUENTIAL=20
>> +DAMAGES
>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS =
OR=20
>> +SERVICES;
>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20=

>> +CAUSED AND
>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT =
LIABILITY,=20
>> +OR TORT
>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20=

>> +USE OF THIS
>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> + */
>> +
>> +/include/ "fsl/b4860si-pre.dtsi"
>> +
>> +/ {
>> +	model =3D "fsl,B4860QDS";
>> +	compatible =3D "fsl,B4860QDS";
>> +	#address-cells =3D <2>;
>> +	#size-cells =3D <2>;
>> +	interrupt-parent =3D <&mpic>;
>> +
>> +	ifc: localbus@ffe124000 {
>> +		reg =3D <0xf 0xfe124000 0 0x2000>;
>> +		ranges =3D <0 0 0xf 0xe8000000 0x08000000
>> +			  2 0 0xf 0xff800000 0x00010000
>> +			  3 0 0xf 0xffdf0000 0x00008000>;
>> +
>> +		nor@0,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "cfi-flash";
>> +			reg =3D <0x0 0x0 0x8000000>;
>> +			bank-width =3D <2>;
>> +			device-width =3D <1>;
>> +		};
>> +
>> +		nand@2,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "fsl,ifc-nand";
>> +			reg =3D <0x2 0x0 0x10000>;
>> +
>> +			partition@0 {
>> +				/* This location must not be altered  */
>> +				/* 1MB for u-boot Bootloader Image */
>> +				reg =3D <0x0 0x00100000>;
>> +				label =3D "NAND U-Boot Image";
>> +				read-only;
>> +			};
>> +
>> +			partition@100000 {
>> +				/* 1MB for DTB Image */
>> +				reg =3D <0x00100000 0x00100000>;
>> +				label =3D "NAND DTB Image";
>> +			};
>> +
>> +			partition@200000 {
>> +				/* 10MB for Linux Kernel Image */
>> +				reg =3D <0x00200000 0x00A00000>;
>> +				label =3D "NAND Linux Kernel Image";
>> +			};
>> +
>> +			partition@c00000 {
>> +				/* 500MB for Root file System Image */
>> +				reg =3D <0x00c00000 0x1F400000>;
>> +				label =3D "NAND RFS Image";
>> +			};
>> +		};
>> +
>> +		board-control@3,0 {
>> +			compatible =3D "fsl,b4860qds-fpga", =
"fsl,fpga-qixis";
>> +			reg =3D <3 0 0x300>;
>> +		};
>> +	};
>> +
>=20
> dscr nodes are missing and should be included
> [SL] I don't have much idea about dcsr nodes structure and their =
respective testing, also couldn't find then in T4 device tree files. I =
have added initial device trees. Dcsr may be added later as updation. =
What do you say? =20

I'll add them to T4, but if you look at the internal FSL SDK tree you =
will see they've been added for T4 & B4.

>=20
>=20
>> +	memory {
>> +		device_type =3D "memory";
>> +	};
>> +
>> +	soc: soc@ffe000000 {
>> +		ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
>> +		reg =3D <0xf 0xfe000000 0 0x00001000>;
>> +		spi@110000 {
>> +			flash@0 {
>> +				#address-cells =3D <1>;
>> +				#size-cells =3D <1>;
>> +				compatible =3D "sst,sst25wf040";
>> +				reg =3D <0>;
>> +				spi-max-frequency =3D <40000000>; /* =
input clock */
>> +			};
>> +		};
>> +
>> +		sdhc@114000 {
>> +			status =3D "disabled";
>> +		};
>> +
>> +		i2c@118000 {
>> +			eeprom@50 {
>> +				compatible =3D "at24,24c64";
>> +				reg =3D <0x50>;
>> +			};
>> +			eeprom@51 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x51>;
>> +			};
>> +			eeprom@53 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x53>;
>> +			};
>> +			eeprom@57 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x57>;
>> +			};
>> +			rtc@68 {
>> +				compatible =3D "dallas,ds3232";
>> +				reg =3D <0x68>;
>> +				interrupts =3D <0x1 0x1 0 0>;
>=20
> there is no IRQ for RTC on the board.
> [SL] will remove it.=20
>=20
>> +			};
>> +		};
>> +
>> +		usb@210000 {
>> +			dr_mode =3D "host";
>> +			phy_type =3D "ulpi";
>> +		};
>> +
>> +	};
>> +
>> +	pci0: pcie@ffe200000 {
>> +		reg =3D <0xf 0xfe200000 0 0x10000>;
>> +		ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 =
0x20000000
>> +			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 =
0x00010000>;
>> +		pcie@0 {
>> +			ranges =3D <0x02000000 0 0xe0000000
>> +				  0x02000000 0 0xe0000000
>> +				  0 0x20000000
>> +
>> +				  0x01000000 0 0x00000000
>> +				  0x01000000 0 0x00000000
>> +				  0 0x00010000>;
>> +		};
>> +	};
>> +
>> +	rio: rapidio@ffe0c0000 {
>> +		reg =3D <0xf 0xfe0c0000 0 0x11000>;
>> +
>> +		port1 {
>> +			ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
>> +		};
>> +		port2 {
>> +			ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
>> +		};
>> +	};
>> +
>> +};
>> +
>> +/include/ "fsl/b4860si-post.dtsi"
>> --
>> 1.7.6.GIT
>>=20
>=20
>=20
> Regards,
> Shaveta
>=20
>=20

Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Kumar Gala]

On Mar 18, 2013, at 2:41 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Timur Tabi [mailto:timur@tabi.org]=20
> Sent: Friday, March 15, 2013 6:38 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian =
Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh =
Ramneek-B31383; Sethi Varun-B16395
> Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device =
tree files for B4860QDS
>=20
> On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha =
<shaveta@freescale.com> wrote:
>=20
>=20
>> +       iommu@20000 {
>> +               compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
>> +               reg =3D <0x20000 0x4000>;
>> +               interrupts =3D <
>> +                       24 2 0 0
>> +                       16 2 1 1>;
>> +       };
>=20
> You need to add the PAMU topology.
> [SL] Thanks for reviewing the patches.
> These patches are on similar lines as T4 initial support
> In due course of time, we plan to add pamu topology and pamu related =
support in various devices both for T4 and B4.
> Kumar can you please suggest?

I can help with the B4 topology as its reasonable well described, I've =
been working on trying to get the info to finish T4.

- k=

RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:26 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support


On Mar 18, 2013, at 1:28 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Friday, March 15, 2013 9:28 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
>=20
>> - Add support for B4 board's personalities in board file  b4_qds.c,=20
>> It is common for B4 personalities B4860 and B4420QDS
>> - Add B4QDS support in Kconfig and Makefile
>=20
> Code also references a B4220, what about it?
> [SL] I have added the basic support for it in board file as it's one=20
> of the personality of B4, missed it in description. But device trees for =
this has not been created and tested.
> So what do you suggest here:
> Should I add it here in B4 board support or should I remove its reference=
s altogether?

What's the difference between B4220 and B4420 or B4860?

- k
[SL] B4220 is again a reduced personality of B4 with some differences like:
	Even lesser Number of cores than B4860 and B4420, lesser number of SerDes =
lanes and some difference in 	other peripherals.
=09
BR,
Shaveta

>=20
>>=20
>> B4860QDS is a high-performance computing evaluation, development and=20
>> test platform supporting the B4860 QorIQ Power Architecture=20
>> processor, with following major features:
>>=20
>>   - Four dual-threaded e6500 Power Architecture processors
>>     organized in one cluster-each core runs up to 1.8 GHz
>>   - Two DDR3/3L controllers for high-speed memory interface each
>>     runs at up to 1866.67 MHz
>>   - CoreNet fabric that fully supports coherency using MESI protocol
>>     between the e6500 cores, SC3900 FVP cores, memories and
>>     external interfaces.
>>   - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3=
 and RMAN
>>   - Large internal cache memory with snooping and stashing capabilities
>>   - Sixteen 10-GHz SerDes lanes that serve:
>>       - Two SRIO interfaces. Each supports up to 4 lanes and
>>         a total of up to 8 lanes
>>       - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>>         for glue-less antenna connection
>>       - Two 10-Gbit Ethernet controllers (10GEC)
>>       - Six 1G/2.5-Gbit Ethernet controllers for network communications
>>       - PCI Express controller
>>       - Debug (Aurora)
>>   - Various system peripherals
>>=20
>> B4420 is a reduced personality of B4860 with fewer core/clusters(both=20
>> SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMI=
I interfaces and reduced target frequencies.
>>=20
>> Key differences between B4860 and B4420:
>> B4420 has:
>>   - Fewer e6500 cores:
>>       1 cluster with 2 e6500 cores
>>   - Fewer SC3900 cores/clusters:
>>       1 cluster with 2 SC3900 cores per cluster
>>   - Single DDRC
>>   - 2X 4 lane serdes
>>   - 3 SGMII interfaces
>>   - no sRIO
>>   - no 10G
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> ---
>> arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
>> arch/powerpc/platforms/85xx/Makefile |    1 +
>> arch/powerpc/platforms/85xx/b4_qds.c |  102
>> ++++++++++++++++++++++++++++++++++
>> 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644=20
>> arch/powerpc/platforms/85xx/b4_qds.c

RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:33 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEM=
ING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board devi=
ce tree


On Mar 18, 2013, at 1:31 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Saturday, March 16, 2013 1:57 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming=20
> Andy-AFLEMING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
> Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board=20
> device tree
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> arch/powerpc/boot/dts/b4860qds.dts |  178
>> ++++++++++++++++++++++++++++++++++++
>> 1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644=20
>> arch/powerpc/boot/dts/b4860qds.dts
>>=20
>> diff --git a/arch/powerpc/boot/dts/b4860qds.dts
>> b/arch/powerpc/boot/dts/b4860qds.dts
>> new file mode 100644
>> index 0000000..ae6ac05
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/b4860qds.dts
>> @@ -0,0 +1,178 @@
>> +/*
>> + * B4860DS Device Tree Source
>> + *
>> + * Copyright 2012 Freescale Semiconductor Inc.
>> + *
>> + * Redistribution and use in source and binary forms, with or=20
>> +without
>> + * modification, are permitted provided that the following conditions a=
re met:
>> + *     * Redistributions of source code must retain the above copyright
>> + *       notice, this list of conditions and the following disclaimer.
>> + *     * Redistributions in binary form must reproduce the above copyri=
ght
>> + *       notice, this list of conditions and the following disclaimer i=
n the
>> + *       documentation and/or other materials provided with the distrib=
ution.
>> + *     * Neither the name of Freescale Semiconductor nor the
>> + *       names of its contributors may be used to endorse or promote pr=
oducts
>> + *       derived from this software without specific prior written perm=
ission.
>> + *
>> + *
>> + * ALTERNATIVELY, this software may be distributed under the terms=20
>> +of the
>> + * GNU General Public License ("GPL") as published by the Free=20
>> +Software
>> + * Foundation, either version 2 of that License or (at your option)=20
>> +any
>> + * later version.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''=20
>> +AND ANY
>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
>> +IMPLIED
>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR=20
>> +PURPOSE ARE
>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
>> +FOR ANY
>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR=20
>> +CONSEQUENTIAL DAMAGES
>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS=20
>> +OR SERVICES;
>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
>> +CAUSED AND
>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT=20
>> +LIABILITY, OR TORT
>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
>> +USE OF THIS
>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> + */
>> +
>> +/include/ "fsl/b4860si-pre.dtsi"
>> +
>> +/ {
>> +	model =3D "fsl,B4860QDS";
>> +	compatible =3D "fsl,B4860QDS";
>> +	#address-cells =3D <2>;
>> +	#size-cells =3D <2>;
>> +	interrupt-parent =3D <&mpic>;
>> +
>> +	ifc: localbus@ffe124000 {
>> +		reg =3D <0xf 0xfe124000 0 0x2000>;
>> +		ranges =3D <0 0 0xf 0xe8000000 0x08000000
>> +			  2 0 0xf 0xff800000 0x00010000
>> +			  3 0 0xf 0xffdf0000 0x00008000>;
>> +
>> +		nor@0,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "cfi-flash";
>> +			reg =3D <0x0 0x0 0x8000000>;
>> +			bank-width =3D <2>;
>> +			device-width =3D <1>;
>> +		};
>> +
>> +		nand@2,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "fsl,ifc-nand";
>> +			reg =3D <0x2 0x0 0x10000>;
>> +
>> +			partition@0 {
>> +				/* This location must not be altered  */
>> +				/* 1MB for u-boot Bootloader Image */
>> +				reg =3D <0x0 0x00100000>;
>> +				label =3D "NAND U-Boot Image";
>> +				read-only;
>> +			};
>> +
>> +			partition@100000 {
>> +				/* 1MB for DTB Image */
>> +				reg =3D <0x00100000 0x00100000>;
>> +				label =3D "NAND DTB Image";
>> +			};
>> +
>> +			partition@200000 {
>> +				/* 10MB for Linux Kernel Image */
>> +				reg =3D <0x00200000 0x00A00000>;
>> +				label =3D "NAND Linux Kernel Image";
>> +			};
>> +
>> +			partition@c00000 {
>> +				/* 500MB for Root file System Image */
>> +				reg =3D <0x00c00000 0x1F400000>;
>> +				label =3D "NAND RFS Image";
>> +			};
>> +		};
>> +
>> +		board-control@3,0 {
>> +			compatible =3D "fsl,b4860qds-fpga", "fsl,fpga-qixis";
>> +			reg =3D <3 0 0x300>;
>> +		};
>> +	};
>> +
>=20
> dscr nodes are missing and should be included [SL] I don't have much=20
> idea about dcsr nodes structure and their respective testing, also couldn=
't find then in T4 device tree files. I have added initial device trees. Dc=
sr may be added later as updation. What do you say?

I'll add them to T4, but if you look at the internal FSL SDK tree you will =
see they've been added for T4 & B4.
[SL] Ok, will add them.
>=20
>=20
>> +	memory {
>> +		device_type =3D "memory";
>> +	};
>> +
>> +	soc: soc@ffe000000 {
>> +		ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
>> +		reg =3D <0xf 0xfe000000 0 0x00001000>;
>> +		spi@110000 {
>> +			flash@0 {
>> +				#address-cells =3D <1>;
>> +				#size-cells =3D <1>;
>> +				compatible =3D "sst,sst25wf040";
>> +				reg =3D <0>;
>> +				spi-max-frequency =3D <40000000>; /* input clock */
>> +			};
>> +		};
>> +
>> +		sdhc@114000 {
>> +			status =3D "disabled";
>> +		};
>> +
>> +		i2c@118000 {
>> +			eeprom@50 {
>> +				compatible =3D "at24,24c64";
>> +				reg =3D <0x50>;
>> +			};
>> +			eeprom@51 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x51>;
>> +			};
>> +			eeprom@53 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x53>;
>> +			};
>> +			eeprom@57 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x57>;
>> +			};
>> +			rtc@68 {
>> +				compatible =3D "dallas,ds3232";
>> +				reg =3D <0x68>;
>> +				interrupts =3D <0x1 0x1 0 0>;
>=20
> there is no IRQ for RTC on the board.
> [SL] will remove it.=20
>=20
>> +			};
>> +		};
>> +
>> +		usb@210000 {
>> +			dr_mode =3D "host";
>> +			phy_type =3D "ulpi";
>> +		};
>> +
>> +	};
>> +
>> +	pci0: pcie@ffe200000 {
>> +		reg =3D <0xf 0xfe200000 0 0x10000>;
>> +		ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
>> +			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
>> +		pcie@0 {
>> +			ranges =3D <0x02000000 0 0xe0000000
>> +				  0x02000000 0 0xe0000000
>> +				  0 0x20000000
>> +
>> +				  0x01000000 0 0x00000000
>> +				  0x01000000 0 0x00000000
>> +				  0 0x00010000>;
>> +		};
>> +	};
>> +
>> +	rio: rapidio@ffe0c0000 {
>> +		reg =3D <0xf 0xfe0c0000 0 0x11000>;
>> +
>> +		port1 {
>> +			ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
>> +		};
>> +		port2 {
>> +			ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
>> +		};
>> +	};
>> +
>> +};
>> +
>> +/include/ "fsl/b4860si-post.dtsi"
>> --
>> 1.7.6.GIT
>>=20
>=20
>=20
> Regards,
> Shaveta
>=20
>=20

RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Leekha Shaveta-B20052]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:34 PM
To: Leekha Shaveta-B20052
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Mi=
nghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek=
-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860QDS


On Mar 18, 2013, at 2:41 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Timur Tabi [mailto:timur@tabi.org]
> Sent: Friday, March 15, 2013 6:38 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
> Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh=20
> Ramneek-B31383; Sethi Varun-B16395
> Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860QDS
>=20
> On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha <shaveta@freescale.com> w=
rote:
>=20
>=20
>> +       iommu@20000 {
>> +               compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
>> +               reg =3D <0x20000 0x4000>;
>> +               interrupts =3D <
>> +                       24 2 0 0
>> +                       16 2 1 1>;
>> +       };
>=20
> You need to add the PAMU topology.
> [SL] Thanks for reviewing the patches.
> These patches are on similar lines as T4 initial support In due course=20
> of time, we plan to add pamu topology and pamu related support in various=
 devices both for T4 and B4.
> Kumar can you please suggest?

I can help with the B4 topology as its reasonable well described, I've been=
 working on trying to get the info to finish T4.
[SL] I have seen your patches to add PAMU topology in B4. Should I include =
them in my set of patches or you would send them above my initial set of pa=
tches?
BR,
Shaveta
- k

RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board device tree

[Leekha Shaveta-B20052]

-----Original Message-----
From: Leekha Shaveta-B20052=20
Sent: Tuesday, March 19, 2013 11:41 AM
To: 'Kumar Gala'
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEM=
ING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: RE: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board devi=
ce tree



-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:33 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming Andy-AFLEM=
ING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board devi=
ce tree


On Mar 18, 2013, at 1:31 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Saturday, March 16, 2013 1:57 AM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Lian Minghuan-B31939; Fleming=20
> Andy-AFLEMING; Aggrwal Poonam-B10812; Mehresh Ramneek-B31383
> Subject: Re: [PATCH 2/6] powerpc/fsl-booke: Add initial B4860QDS board=20
> device tree
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> arch/powerpc/boot/dts/b4860qds.dts |  178
>> ++++++++++++++++++++++++++++++++++++
>> 1 files changed, 178 insertions(+), 0 deletions(-) create mode 100644=20
>> arch/powerpc/boot/dts/b4860qds.dts
>>=20
>> diff --git a/arch/powerpc/boot/dts/b4860qds.dts
>> b/arch/powerpc/boot/dts/b4860qds.dts
>> new file mode 100644
>> index 0000000..ae6ac05
>> --- /dev/null
>> +++ b/arch/powerpc/boot/dts/b4860qds.dts
>> @@ -0,0 +1,178 @@
>> +/*
>> + * B4860DS Device Tree Source
>> + *
>> + * Copyright 2012 Freescale Semiconductor Inc.
>> + *
>> + * Redistribution and use in source and binary forms, with or=20
>> +without
>> + * modification, are permitted provided that the following conditions a=
re met:
>> + *     * Redistributions of source code must retain the above copyright
>> + *       notice, this list of conditions and the following disclaimer.
>> + *     * Redistributions in binary form must reproduce the above copyri=
ght
>> + *       notice, this list of conditions and the following disclaimer i=
n the
>> + *       documentation and/or other materials provided with the distrib=
ution.
>> + *     * Neither the name of Freescale Semiconductor nor the
>> + *       names of its contributors may be used to endorse or promote pr=
oducts
>> + *       derived from this software without specific prior written perm=
ission.
>> + *
>> + *
>> + * ALTERNATIVELY, this software may be distributed under the terms=20
>> +of the
>> + * GNU General Public License ("GPL") as published by the Free=20
>> +Software
>> + * Foundation, either version 2 of that License or (at your option)=20
>> +any
>> + * later version.
>> + *
>> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS''=20
>> +AND ANY
>> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE=20
>> +IMPLIED
>> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR=20
>> +PURPOSE ARE
>> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE=20
>> +FOR ANY
>> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR=20
>> +CONSEQUENTIAL DAMAGES
>> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS=20
>> +OR SERVICES;
>> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER=20
>> +CAUSED AND
>> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT=20
>> +LIABILITY, OR TORT
>> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE=20
>> +USE OF THIS
>> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> + */
>> +
>> +/include/ "fsl/b4860si-pre.dtsi"
>> +
>> +/ {
>> +	model =3D "fsl,B4860QDS";
>> +	compatible =3D "fsl,B4860QDS";
>> +	#address-cells =3D <2>;
>> +	#size-cells =3D <2>;
>> +	interrupt-parent =3D <&mpic>;
>> +
>> +	ifc: localbus@ffe124000 {
>> +		reg =3D <0xf 0xfe124000 0 0x2000>;
>> +		ranges =3D <0 0 0xf 0xe8000000 0x08000000
>> +			  2 0 0xf 0xff800000 0x00010000
>> +			  3 0 0xf 0xffdf0000 0x00008000>;
>> +
>> +		nor@0,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "cfi-flash";
>> +			reg =3D <0x0 0x0 0x8000000>;
>> +			bank-width =3D <2>;
>> +			device-width =3D <1>;
>> +		};
>> +
>> +		nand@2,0 {
>> +			#address-cells =3D <1>;
>> +			#size-cells =3D <1>;
>> +			compatible =3D "fsl,ifc-nand";
>> +			reg =3D <0x2 0x0 0x10000>;
>> +
>> +			partition@0 {
>> +				/* This location must not be altered  */
>> +				/* 1MB for u-boot Bootloader Image */
>> +				reg =3D <0x0 0x00100000>;
>> +				label =3D "NAND U-Boot Image";
>> +				read-only;
>> +			};
>> +
>> +			partition@100000 {
>> +				/* 1MB for DTB Image */
>> +				reg =3D <0x00100000 0x00100000>;
>> +				label =3D "NAND DTB Image";
>> +			};
>> +
>> +			partition@200000 {
>> +				/* 10MB for Linux Kernel Image */
>> +				reg =3D <0x00200000 0x00A00000>;
>> +				label =3D "NAND Linux Kernel Image";
>> +			};
>> +
>> +			partition@c00000 {
>> +				/* 500MB for Root file System Image */
>> +				reg =3D <0x00c00000 0x1F400000>;
>> +				label =3D "NAND RFS Image";
>> +			};
>> +		};
>> +
>> +		board-control@3,0 {
>> +			compatible =3D "fsl,b4860qds-fpga", "fsl,fpga-qixis";
>> +			reg =3D <3 0 0x300>;
>> +		};
>> +	};
>> +
>=20
> dscr nodes are missing and should be included [SL] I don't have much=20
> idea about dcsr nodes structure and their respective testing, also couldn=
't find then in T4 device tree files. I have added initial device trees. Dc=
sr may be added later as updation. What do you say?

I'll add them to T4, but if you look at the internal FSL SDK tree you will =
see they've been added for T4 & B4.
[SL] Ok, will add them.

Can you please point me to the patch or codebase where dcsr nodes are added=
 in B4?=20
BR,
Shaveta


>=20
>=20
>> +	memory {
>> +		device_type =3D "memory";
>> +	};
>> +
>> +	soc: soc@ffe000000 {
>> +		ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
>> +		reg =3D <0xf 0xfe000000 0 0x00001000>;
>> +		spi@110000 {
>> +			flash@0 {
>> +				#address-cells =3D <1>;
>> +				#size-cells =3D <1>;
>> +				compatible =3D "sst,sst25wf040";
>> +				reg =3D <0>;
>> +				spi-max-frequency =3D <40000000>; /* input clock */
>> +			};
>> +		};
>> +
>> +		sdhc@114000 {
>> +			status =3D "disabled";
>> +		};
>> +
>> +		i2c@118000 {
>> +			eeprom@50 {
>> +				compatible =3D "at24,24c64";
>> +				reg =3D <0x50>;
>> +			};
>> +			eeprom@51 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x51>;
>> +			};
>> +			eeprom@53 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x53>;
>> +			};
>> +			eeprom@57 {
>> +				compatible =3D "at24,24c256";
>> +				reg =3D <0x57>;
>> +			};
>> +			rtc@68 {
>> +				compatible =3D "dallas,ds3232";
>> +				reg =3D <0x68>;
>> +				interrupts =3D <0x1 0x1 0 0>;
>=20
> there is no IRQ for RTC on the board.
> [SL] will remove it.=20
>=20
>> +			};
>> +		};
>> +
>> +		usb@210000 {
>> +			dr_mode =3D "host";
>> +			phy_type =3D "ulpi";
>> +		};
>> +
>> +	};
>> +
>> +	pci0: pcie@ffe200000 {
>> +		reg =3D <0xf 0xfe200000 0 0x10000>;
>> +		ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
>> +			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
>> +		pcie@0 {
>> +			ranges =3D <0x02000000 0 0xe0000000
>> +				  0x02000000 0 0xe0000000
>> +				  0 0x20000000
>> +
>> +				  0x01000000 0 0x00000000
>> +				  0x01000000 0 0x00000000
>> +				  0 0x00010000>;
>> +		};
>> +	};
>> +
>> +	rio: rapidio@ffe0c0000 {
>> +		reg =3D <0xf 0xfe0c0000 0 0x11000>;
>> +
>> +		port1 {
>> +			ranges =3D <0 0 0xc 0x20000000 0 0x10000000>;
>> +		};
>> +		port2 {
>> +			ranges =3D <0 0 0xc 0x30000000 0 0x10000000>;
>> +		};
>> +	};
>> +
>> +};
>> +
>> +/include/ "fsl/b4860si-post.dtsi"
>> --
>> 1.7.6.GIT
>>=20
>=20
>=20
> Regards,
> Shaveta
>=20
>=20

RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Leekha Shaveta-B20052]

-----Original Message-----
From: Leekha Shaveta-B20052=20
Sent: Tuesday, March 19, 2013 11:43 AM
To: 'Kumar Gala'
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Mi=
nghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek=
-B31383; Sethi Varun-B16395
Subject: RE: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860QDS



-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:34 PM
To: Leekha Shaveta-B20052
Cc: Timur Tabi; linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Mi=
nghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek=
-B31383; Sethi Varun-B16395
Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree=
 files for B4860QDS


On Mar 18, 2013, at 2:41 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Timur Tabi [mailto:timur@tabi.org]
> Sent: Friday, March 15, 2013 6:38 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
> Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh=20
> Ramneek-B31383; Sethi Varun-B16395
> Subject: Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860QDS
>=20
> On Fri, Mar 15, 2013 at 2:55 AM, Shaveta Leekha <shaveta@freescale.com> w=
rote:
>=20
>=20
>> +       iommu@20000 {
>> +               compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
>> +               reg =3D <0x20000 0x4000>;
>> +               interrupts =3D <
>> +                       24 2 0 0
>> +                       16 2 1 1>;
>> +       };
>=20
> You need to add the PAMU topology.
> [SL] Thanks for reviewing the patches.
> These patches are on similar lines as T4 initial support In due course=20
> of time, we plan to add pamu topology and pamu related support in various=
 devices both for T4 and B4.
> Kumar can you please suggest?

I can help with the B4 topology as its reasonable well described, I've been=
 working on trying to get the info to finish T4.
[SL] I have seen your patches to add PAMU topology in B4. Should I include =
them in my set of patches or you would send them above my initial set of pa=
tches?
BR,
Shaveta
[SL] Kumar, Waiting for your response on it. Thought I have sent new set of=
 patches with the refactoring suggested, but not added PAMU in them.

BR,
Shaveta

Re: [PATCH 1/6] powerpc/fsl-booke: Add initial silicon device tree files for B4860QDS

[Timur Tabi]

Leekha Shaveta-B20052 wrote:
> [SL] Kumar, Waiting for your response on it. Thought I have sent new
> set of patches with the refactoring suggested, but not added PAMU in
> them.

If you have the information, why wouldn't you include it in the patch? 
The hard part has already been done for you!

-- 
Timur Tabi