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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b001c779e82af6sm5758617pjf.48.2022.04.15.19.26.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Apr 2022 19:26:29 -0700 (PDT) Message-ID: <7878fbf7-6352-fe32-1daa-272490fe8061@linaro.org> Date: Fri, 15 Apr 2022 19:26:27 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v1 26/43] target/loongarch: Add LoongArch IOCSR instruction Content-Language: en-US To: Xiaojuan Yang , qemu-devel@nongnu.org References: <20220415094058.3584233-1-yangxiaojuan@loongson.cn> <20220415094058.3584233-27-yangxiaojuan@loongson.cn> From: Richard Henderson In-Reply-To: <20220415094058.3584233-27-yangxiaojuan@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, gaosong@loongson.cn Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/15/22 02:40, Xiaojuan Yang wrote: > +static bool trans_iocsrrd_b(DisasContext *ctx, arg_iocsrrd_b *a) > +static bool trans_iocsrrd_h(DisasContext *ctx, arg_iocsrrd_h *a) > +static bool trans_iocsrrd_w(DisasContext *ctx, arg_iocsrrd_w *a) > +static bool trans_iocsrrd_d(DisasContext *ctx, arg_iocsrrd_d *a) You have all of these split apart, then pass an integer to a common routine... > +uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr, > + uint32_t size) > +{ > + int cpuid = env_cpu(env)->cpu_index; > + CPUState *cs = qemu_get_cpu(cpuid); > + env = cs->env_ptr; > + uint64_t ret = 0; > + > + /* > + * Adjust the per core address such as 0x10xx(IPI)/0x18xx(EXTIOI) > + */ > + if (((r_addr & 0xff00) == 0x1000) || ((r_addr & 0xff00) == 0x1800)) { > + r_addr = r_addr + ((target_ulong)(cpuid & 0x3) << 8); > + } > + > + switch (size) { > + case 1: > + ret = address_space_ldub(&env->address_space_iocsr, r_addr, > + MEMTXATTRS_UNSPECIFIED, NULL); > + break; > + case 2: > + ret = address_space_lduw(&env->address_space_iocsr, r_addr, > + MEMTXATTRS_UNSPECIFIED, NULL); > + break; > + case 4: > + ret = address_space_ldl(&env->address_space_iocsr, r_addr, > + MEMTXATTRS_UNSPECIFIED, NULL); > + break; > + case 8: > + ret = address_space_ldq(&env->address_space_iocsr, r_addr, > + MEMTXATTRS_UNSPECIFIED, NULL); > + break; > + default: > + g_assert_not_reached(); > + } ... then have to split them apart again. It would be cleaner to have 4 helpers, one for each size. I'm concerned about the address adjustment. My thinking is that this should be handled by the address space (via a MemoryRegionOps entry). I say this because there is nothing about this adjustment in "LoongArch Reference Manual", but rather in the "LoongArch 3A5000 Registers Technical Reference Manual". Which means that baking this cpu specific behaviour into the generic architecture is incorrect. > +void helper_iocsr_write(CPULoongArchState *env, target_ulong w_addr, > + target_ulong val, uint32_t size) > +{ > + int cpuid = env_cpu(env)->cpu_index; > + CPUState *cs = qemu_get_cpu(cpuid); > + int mask, i; > + env = cs->env_ptr; > + > + /* > + * For IPI send, Mailbox send and ANY send, adjust the addr and > + * val accordingly. The IOCSR writes are turned to different > + * MMIO writes respectively > + */ > + switch (w_addr) { > + case 0x1040: /* IPI send */ Likewise. r~