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[2603:800c:3202:ffa7:497b:6ae4:953c:7ad1]) by smtp.gmail.com with ESMTPSA id t19sm16674870pfg.216.2021.07.25.11.14.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 25 Jul 2021 11:14:48 -0700 (PDT) Subject: Re: [PATCH for-6.1 1/6] target/arm: Enforce that M-profile SP low 2 bits are always zero To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210723162146.5167-1-peter.maydell@linaro.org> <20210723162146.5167-2-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <78c107f3-23ac-3279-99e1-84df8c5498b8@linaro.org> Date: Sun, 25 Jul 2021 08:14:46 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210723162146.5167-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/23/21 6:21 AM, Peter Maydell wrote: > For M-profile, unlike A-profile, the low 2 bits of SP are defined to be > RES0H, which is to say that they must be hardwired to zero so that > guest attempts to write non-zero values to them are ignored. > > Implement this behaviour by masking out the low bits: > * for writes to r13 by the gdbstub > * for writes to any of the various flavours of SP via MSR > * for writes to r13 via store_reg() in generated code > > Note that all the direct uses of cpu_R[] in translate.c are in places > where the register is definitely not r13 (usually because that has > been checked for as an UNDEFINED or UNPREDICTABLE case and handled as > UNDEF). > > All the other writes to regs[13] in C code are either: > * A-profile only code > * writes of values we can guarantee to be aligned, such as > - writes of previous-SP-value plus or minus a 4-aligned constant > - writes of the value in an SP limit register (which we already > enforce to be aligned) > > Signed-off-by: Peter Maydell > --- Reviewed-by: Richard Henderson r~