From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bui Duc Phuc Date: Mon, 12 Sep 2016 15:12:08 +0000 Subject: Re: [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings Message-Id: <7916c4bd-94a1-0d87-e2dc-2fd852976cfc@jinso.co.jp> List-Id: References: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> <1473421394-9745-2-git-send-email-bd-phuc@jinso.co.jp> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-arm-kernel@lists.infradead.org Dear Geert, > I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do > not allow to differentiate between CMT0 and CMT1, which have different feature > sets. > > Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" > (https://lkml.org/lkml/2016/3/14/433). > > Magnus: What's the status of your series? Thank for your comments. I will update in V2. I am still waiting for Magnus's comments, but from my point of view,Magnus's patches seem support 32 bit counter only, they are not suitable for 48bit counter. According to hardware manual, there has to be registers ( CMCSRH, CMCNTH,CMCORH) set for 48 bit counter, but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches. -- Regards, Bui Duc Phuc From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bui Duc Phuc Subject: Re: [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings Date: Tue, 13 Sep 2016 00:12:08 +0900 Message-ID: <7916c4bd-94a1-0d87-e2dc-2fd852976cfc@jinso.co.jp> References: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> <1473421394-9745-2-git-send-email-bd-phuc@jinso.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-sh-owner@vger.kernel.org To: Geert Uytterhoeven , Magnus Damm Cc: Daniel Lezcano , Thomas Gleixner , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linux-sh list , Geert Uytterhoeven , Linux-Renesas , linux-arm-kernel@vger.kernel.org, Laurent Pinchart , Simon Horman , Kuninori Morimoto , Yoshihiro Shimoda , Ryusuke Sakato , =?UTF-8?B?56iy5ZCJ?= , Cao Minh Hiep , =?UTF-8?B?RHVuZ++8muS6uuOCvQ==?= List-Id: devicetree@vger.kernel.org Dear Geert, > I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do > not allow to differentiate between CMT0 and CMT1, which have different feature > sets. > > Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" > (https://lkml.org/lkml/2016/3/14/433). > > Magnus: What's the status of your series? Thank for your comments. I will update in V2. I am still waiting for Magnus's comments, but from my point of view,Magnus's patches seem support 32 bit counter only, they are not suitable for 48bit counter. According to hardware manual, there has to be registers ( CMCSRH, CMCNTH,CMCORH) set for 48 bit counter, but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches. -- Regards, Bui Duc Phuc From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings To: Geert Uytterhoeven , Magnus Damm References: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> <1473421394-9745-2-git-send-email-bd-phuc@jinso.co.jp> Cc: Daniel Lezcano , Thomas Gleixner , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linux-sh list , Geert Uytterhoeven , Linux-Renesas , linux-arm-kernel@vger.kernel.org, Laurent Pinchart , Simon Horman , Kuninori Morimoto , Yoshihiro Shimoda , Ryusuke Sakato , =?UTF-8?B?56iy5ZCJ?= , Cao Minh Hiep , =?UTF-8?B?RHVuZ++8muS6uuOCvQ==?= From: Bui Duc Phuc Message-ID: <7916c4bd-94a1-0d87-e2dc-2fd852976cfc@jinso.co.jp> Date: Tue, 13 Sep 2016 00:12:08 +0900 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org List-ID: Dear Geert, > I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do > not allow to differentiate between CMT0 and CMT1, which have different feature > sets. > > Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" > (https://lkml.org/lkml/2016/3/14/433). > > Magnus: What's the status of your series? Thank for your comments. I will update in V2. I am still waiting for Magnus's comments, but from my point of view,Magnus's patches seem support 32 bit counter only, they are not suitable for 48bit counter. According to hardware manual, there has to be registers ( CMCSRH, CMCNTH,CMCORH) set for 48 bit counter, but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches. -- Regards, Bui Duc Phuc From mboxrd@z Thu Jan 1 00:00:00 1970 From: bd-phuc@jinso.co.jp (Bui Duc Phuc) Date: Tue, 13 Sep 2016 00:12:08 +0900 Subject: [PATCH 1/8] devicetree: binding: R-car Gen3 CMT0 and CMT1 bindings In-Reply-To: References: <1473421394-9745-1-git-send-email-bd-phuc@jinso.co.jp> <1473421394-9745-2-git-send-email-bd-phuc@jinso.co.jp> Message-ID: <7916c4bd-94a1-0d87-e2dc-2fd852976cfc@jinso.co.jp> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dear Geert, > I think the plan was to get rid of the renesas,cmt-48-* bindings, as they do > not allow to differentiate between CMT0 and CMT1, which have different feature > sets. > > Cfr. Magnus' series "clocksource: sh_cmt: DT binding rework V4" > (https://lkml.org/lkml/2016/3/14/433). > > Magnus: What's the status of your series? Thank for your comments. I will update in V2. I am still waiting for Magnus's comments, but from my point of view,Magnus's patches seem support 32 bit counter only, they are not suitable for 48bit counter. According to hardware manual, there has to be registers ( CMCSRH, CMCNTH,CMCORH) set for 48 bit counter, but I do not see the registers ( CMCSRH, CMCNTH,CMCORH) in Magnus's patches. -- Regards, Bui Duc Phuc