From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D27DC433E0 for ; Thu, 31 Dec 2020 20:56:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A28EB207AF for ; Thu, 31 Dec 2020 20:56:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A28EB207AF Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kv4zM-0004d6-Da for qemu-devel@archiver.kernel.org; Thu, 31 Dec 2020 15:56:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57064) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kv4yR-0003kg-Hc; Thu, 31 Dec 2020 15:55:07 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:35464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kv4yO-0007zW-LE; Thu, 31 Dec 2020 15:55:06 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 7BF657470E4; Thu, 31 Dec 2020 21:55:00 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id E32F67470F2; Thu, 31 Dec 2020 21:54:59 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id E0D6074645F; Thu, 31 Dec 2020 21:54:59 +0100 (CET) Date: Thu, 31 Dec 2020 21:54:59 +0100 (CET) To: Peter Maydell Subject: Re: [PATCH v2 3/3] sam460ex: Clean up irq mapping In-Reply-To: Message-ID: <79681dc2-d689-4518-a83-dead38dd6e8@eik.bme.hu> References: <6892fc8ac57283bf7ba27fe89ea9dbdd6a37f988.1609413115.git.balaton@eik.bme.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , qemu-ppc , QEMU Developers , Guenter Roeck , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via On Thu, 31 Dec 2020, Peter Maydell wrote: > On Thu, 31 Dec 2020 at 15:11, Peter Maydell wrote: >> On Thu, 31 Dec 2020 at 11:20, BALATON Zoltan wrote: >>> >>> Avoid mapping multiple interrupts to the same irq. Instead map them to >>> the 4 PCI interrupts and use an or-gate in the board to connect them >>> to the interrupt controller. This does not fix any known problem but >>> does not seem to cause a new problem either and may be cleaner at least. >>> >>> Signed-off-by: BALATON Zoltan >>> Tested-by: Guenter Roeck >> >> So, this patch is a behavioural change, but I think it's >> probably a change to the right behaviour. The difference >> is relatively slight, but you would see it if there are two >> different PCI cards and they both assert a different PCI >> interrupt, and then one of them lowers the interrupt >> before the other: > > This turns out to be wrong -- I hadn't looked at the QEMU PCI > code, but it has an internal implementation of logic that > gives the same behaviour as an explicit OR gate. Basically > pci_change_irq_level() tracks how many assert/deasserts of > the (mapped) IRQ lines have happened, so it only calls the > controller's set_irq function when the count of asserted > inputs goes down to 0. So both the current code and this > patch's change are functionally correct. I've remembered we had this discussion before and arrived to the same conclusion that current code was equivalently working but could not recall the reason. > I'm not sure which would be nominally closer to the "real hardware": > the 440ex CPU/SoC datasheet lists a single PCI0INT signal, but > it says it is an output, not an input, so I'm pretty sure there's > something I don't understand about PCI here. (Also, unlike the > 440EP it provides PCI Express as well as PCI.) The SoC is called 460EX (despite having a PPC 440 core not 460 one) but I think you've looked at the right data sheet and it's just a typo. I also don't know how the board is wired so I think in this case I prefer dropping this patch and keeping the current code just for simplicity but to avoid going through this again maybe we should add a comment saying why it's working. Can you please suggest a test for such comment pointing to the relevant part of pci_change_irq_level() you refer to above? I don't think I understand it enough to document it. Thank you, BALATON Zoltan