From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932255AbcKUNGu (ORCPT ); Mon, 21 Nov 2016 08:06:50 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:18589 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753918AbcKUNGq (ORCPT ); Mon, 21 Nov 2016 08:06:46 -0500 Subject: Re: [PATCH V5 1/3] ARM64 LPC: Indirect ISA port IO introduced To: Benjamin Herrenschmidt , Mark Rutland , "zhichang.yuan" References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-2-git-send-email-yuanzhichang@hisilicon.com> <20161108120323.GC15297@leverpostej> <1478647002.7430.69.camel@kernel.crashing.org> CC: , , , , , , , , , , , , , , , , , , , , From: John Garry Message-ID: <79d73f93-1cf8-19db-ca5c-8fb6257edd6c@huawei.com> Date: Mon, 21 Nov 2016 12:58:28 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <1478647002.7430.69.camel@kernel.crashing.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.181.152] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/11/2016 23:16, Benjamin Herrenschmidt wrote: > On Tue, 2016-11-08 at 12:03 +0000, Mark Rutland wrote: >> On Tue, Nov 08, 2016 at 11:47:07AM +0800, zhichang.yuan wrote: >>> >>> For arm64, there is no I/O space as other architectural platforms, such as >>> X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs, >>> such as Hip06, when accessing some legacy ISA devices connected to LPC, those >>> known port addresses are used to control the corresponding target devices, for >>> example, 0x2f8 is for UART, 0xe4 is for ipmi-bt. It is different from the >>> normal MMIO mode in using. >> >> This has nothing to do with arm64. Hardware with this kind of indirect >> bus access could be integrated with a variety of CPU architectures. It >> simply hasn't been, yet. > > On some ppc's we also use similar indirect access methods for IOs. We > have a generic infrastructure for re-routing some memory or IO regions > to hooks. > > On POWER8, our PCIe doesn't do IO at all, but we have an LPC bus behind > firmware calls ;-) We use that infrastructure to plumb in the LPC bus. > Hi, I would like to mention another topic on supporting LPC, and this is regard to eSPI support. eSPI is seen as the successor for LPC, and some BMCs already support it. I had a chat with Arnd on this, and the idea to model LPC as a SPI bus adpater (and also eSPI). However it seems to me that most platforms will/should support eSPI as a transparent bridge, same as LPC on x86. So I don't think that this is much point in modelling LPC/eSPI as a bus. So we shall continue with indriect-IO support... Thanks, John From mboxrd@z Thu Jan 1 00:00:00 1970 From: John Garry Subject: Re: [PATCH V5 1/3] ARM64 LPC: Indirect ISA port IO introduced Date: Mon, 21 Nov 2016 12:58:28 +0000 Message-ID: <79d73f93-1cf8-19db-ca5c-8fb6257edd6c@huawei.com> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-2-git-send-email-yuanzhichang@hisilicon.com> <20161108120323.GC15297@leverpostej> <1478647002.7430.69.camel@kernel.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1478647002.7430.69.camel@kernel.crashing.org> Sender: linux-kernel-owner@vger.kernel.org To: Benjamin Herrenschmidt , Mark Rutland , "zhichang.yuan" Cc: catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, bhelgaas@google.com, olof@lixom.net, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, minyard@acm.org, liviu.dudau@arm.com, zourongrong@gmail.com, gabriele.paoloni@huawei.com, zhichang.yuan02@gmail.com, kantyzc@163.com, xuwei5@hisilicon.com, marc.zyngier@arm.com List-Id: devicetree@vger.kernel.org On 08/11/2016 23:16, Benjamin Herrenschmidt wrote: > On Tue, 2016-11-08 at 12:03 +0000, Mark Rutland wrote: >> On Tue, Nov 08, 2016 at 11:47:07AM +0800, zhichang.yuan wrote: >>> >>> For arm64, there is no I/O space as other architectural platforms, such as >>> X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs, >>> such as Hip06, when accessing some legacy ISA devices connected to LPC, those >>> known port addresses are used to control the corresponding target devices, for >>> example, 0x2f8 is for UART, 0xe4 is for ipmi-bt. It is different from the >>> normal MMIO mode in using. >> >> This has nothing to do with arm64. Hardware with this kind of indirect >> bus access could be integrated with a variety of CPU architectures. It >> simply hasn't been, yet. > > On some ppc's we also use similar indirect access methods for IOs. We > have a generic infrastructure for re-routing some memory or IO regions > to hooks. > > On POWER8, our PCIe doesn't do IO at all, but we have an LPC bus behind > firmware calls ;-) We use that infrastructure to plumb in the LPC bus. > Hi, I would like to mention another topic on supporting LPC, and this is regard to eSPI support. eSPI is seen as the successor for LPC, and some BMCs already support it. I had a chat with Arnd on this, and the idea to model LPC as a SPI bus adpater (and also eSPI). However it seems to me that most platforms will/should support eSPI as a transparent bridge, same as LPC on x86. So I don't think that this is much point in modelling LPC/eSPI as a bus. So we shall continue with indriect-IO support... Thanks, John From mboxrd@z Thu Jan 1 00:00:00 1970 From: john.garry@huawei.com (John Garry) Date: Mon, 21 Nov 2016 12:58:28 +0000 Subject: [PATCH V5 1/3] ARM64 LPC: Indirect ISA port IO introduced In-Reply-To: <1478647002.7430.69.camel@kernel.crashing.org> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-2-git-send-email-yuanzhichang@hisilicon.com> <20161108120323.GC15297@leverpostej> <1478647002.7430.69.camel@kernel.crashing.org> Message-ID: <79d73f93-1cf8-19db-ca5c-8fb6257edd6c@huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/11/2016 23:16, Benjamin Herrenschmidt wrote: > On Tue, 2016-11-08 at 12:03 +0000, Mark Rutland wrote: >> On Tue, Nov 08, 2016 at 11:47:07AM +0800, zhichang.yuan wrote: >>> >>> For arm64, there is no I/O space as other architectural platforms, such as >>> X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs, >>> such as Hip06, when accessing some legacy ISA devices connected to LPC, those >>> known port addresses are used to control the corresponding target devices, for >>> example, 0x2f8 is for UART, 0xe4 is for ipmi-bt. It is different from the >>> normal MMIO mode in using. >> >> This has nothing to do with arm64. Hardware with this kind of indirect >> bus access could be integrated with a variety of CPU architectures. It >> simply hasn't been, yet. > > On some ppc's we also use similar indirect access methods for IOs. We > have a generic infrastructure for re-routing some memory or IO regions > to hooks. > > On POWER8, our PCIe doesn't do IO at all, but we have an LPC bus behind > firmware calls ;-) We use that infrastructure to plumb in the LPC bus. > Hi, I would like to mention another topic on supporting LPC, and this is regard to eSPI support. eSPI is seen as the successor for LPC, and some BMCs already support it. I had a chat with Arnd on this, and the idea to model LPC as a SPI bus adpater (and also eSPI). However it seems to me that most platforms will/should support eSPI as a transparent bridge, same as LPC on x86. So I don't think that this is much point in modelling LPC/eSPI as a bus. So we shall continue with indriect-IO support... Thanks, John