From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RvUN8-0003Ej-RP for qemu-devel@nongnu.org; Thu, 09 Feb 2012 08:49:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RvUN4-0003Jo-87 for qemu-devel@nongnu.org; Thu, 09 Feb 2012 08:49:14 -0500 Mime-Version: 1.0 (Apple Message framework v1257) Content-Type: text/plain; charset=us-ascii From: Alexander Graf In-Reply-To: <20120209084339.79536829@BR8GGW75.de.ibm.com> Date: Thu, 9 Feb 2012 14:49:07 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <7A8FD6FF-A346-4EFB-BBE2-D28CD664283B@suse.de> References: <1328680437-31779-1-git-send-email-david@gibson.dropbear.id.au> <20120208104840.GG11852@truffala.fritz.box> <20120208142735.3bbc7cd6@BR8GGW75.de.ibm.com> <20120209002609.GH11852@truffala.fritz.box> <20120209084339.79536829@BR8GGW75.de.ibm.com> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC64: Add support for ldbrx and stdbrx instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Huth Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 09.02.2012, at 08:43, Thomas Huth wrote: > Am Thu, 9 Feb 2012 11:26:09 +1100 > schrieb David Gibson : >=20 >> On Wed, Feb 08, 2012 at 02:27:35PM +0100, Thomas Huth wrote: >>> Am Wed, 8 Feb 2012 21:48:40 +1100 >>> schrieb David Gibson : >>>=20 >>>> On Wed, Feb 08, 2012 at 10:54:21AM +0400, malc wrote: >>>>> On Wed, 8 Feb 2012, David Gibson wrote: >>>>>=20 >>>>>> From: Thomas Huth >>>>>>=20 >>>>>> These instructions for loading and storing byte-swapped 64-bit = values have >>>>>> been introduced in PowerISA 2.06. >>>>>>=20 >>>>>> Signed-off-by: Thomas Huth >>>>>> --- >>>>>> target-ppc/translate.c | 30 ++++++++++++++++++++++++++++++ >>>>>> 1 files changed, 30 insertions(+), 0 deletions(-) >>>>>=20 >>>>> I seem to recall that POWER5 machine i had access to didn't have=20= >>>>> ld/stdbrx while CBE did have it (or was it the other way around?) >>>>> so question is - is PPC_64B sufficient? >>>>=20 >>>> Ah, I think it's not. I think I spotted that before, but then = forgot >>>> about it. Thanks for the reminder. >>>=20 >>> Maybe it's a better idea to use PPC_64BX here? ... but that flag = seems >>> to be missing in POWERPC_INSNS_POWER7... David, could PPC_64BX also = be >>> included in that flag list? >>=20 >> Um.. what exactly do you mean by 64BX? >>=20 >=20 > There is a definition in target-ppc/cpu.h: >=20 > /* New 64 bits extensions (PowerPC 2.0x) */ > PPC_64BX =3D 0x0000000000000040ULL, >=20 > According to the comment, I thought the PPC_64BX might be designed > for new 64-bit instructions? Well, we need to be a bit more specific here to know what we're = implementing. The flag above just indicates the lq opcode: target-ppc/translate.c:GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, = PPC_64BX), So how about we create a new PPC2 flag for BRX and add that in POWER7 = INSNS? If you could find out if Cell also supports these instructions, = that'd be great. I don't have a 2.05 spec handy and 2.04 doesn't = implement it yet. Alex