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Mon, 20 Jun 2022 17:59:12 -0500 From: Ashish Kalra To: , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH Part2 v6 01/49] x86/cpufeatures: Add SEV-SNP CPU feature Date: Mon, 20 Jun 2022 22:59:01 +0000 Message-ID: <7abfca61f8595c036e1bd9f1d65ab78af0006627.1655761627.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5f973712-7a60-4e30-21ab-08da53107f6d X-MS-TrafficTypeDiagnostic: CY5PR12MB6106:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9Whthn3VJlIN8bfO5qQ3CLHshN6fTnueuc372UkcfxwZPB1JFomBnPFnlOdoriy+SmJvcsmoYc53QPwuhISCJ/mp4RrjuVrj9Ev81HPDxj5qWQoBIk9MK99IgVTIMnzdZb0fCp/qEcdiKT4ZM83BemKAUK8Ypc9RFEjM8kM805QGvAxA1MwskCzpmhkyVCTx4C9Kx7LGKIJLvEXveTY9IMIkUIxlE3txVKzi6DMNc7fwJUA5OmGaK3LjLPeM20VNwgoqAUnLhVl4ZbX30lTN/Pg7griLgDMIp6v6AbvtuBUXJ5bAlpthYQfUTfxFQ9LrOoNDC5rRl37rMjYY7rnoLyx3sjqWkM9c1TtMCoolFj9Ur1Fx+215wzhwMqXiDWsy8CwKakRwlH9o6D4T4gdRQOJ6LM88QZlbsv8HZmy11YcYJ4ubyKIydfU52S+H7JIn9v+GfBAqQD56J5p41g9W6wgtx6ppjNes0OTNI5v7T8fRuZZNPhPTr0ganw/cEoW6mN7iELzASfsbxSUjumr7idETW3zsY2TIWAhVLsniXJwfV1lrhAmumUPzgMu7uDdREtdJzpteNLeMLXrh/1q3deg7bRSRCmSOo9W7ZP85234fwM3VwbXhVZhOIunyvO4AuAn2lCRO/hn/dhi8h/9bfGeh9qn8JXEBPLmOcMhLGtoB1QogXXwXqzlBWAZ8coIpsxPReQ1BKAKzkKwAYRs0i3Zk6n+VuLO3MoIFmiriV4l0eEqPDA3PeqAyWUtiTq6DHdteoVX1VaJTKNpSu9c1Qg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(136003)(39860400002)(396003)(376002)(346002)(36840700001)(40470700004)(46966006)(40480700001)(7696005)(36860700001)(6666004)(70586007)(16526019)(26005)(2616005)(478600001)(186003)(70206006)(40460700003)(8936002)(82740400003)(86362001)(336012)(47076005)(36756003)(5660300002)(4326008)(83380400001)(426003)(81166007)(316002)(7416002)(2906002)(41300700001)(8676002)(54906003)(356005)(110136005)(82310400005)(7406005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2022 22:59:14.8162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f973712-7a60-4e30-21ab-08da53107f6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6106 From: Brijesh Singh Add CPU feature detection for Secure Encrypted Virtualization with Secure Nested Paging. This feature adds a strong memory integrity protection to help prevent malicious hypervisor-based attacks like data replay, memory re-mapping, and more. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 3 ++- tools/arch/x86/include/asm/cpufeatures.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 30da1341f226..1cba0217669f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -407,6 +407,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0c0b09796ced..2e87015a9d69 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -559,7 +559,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) * If the kernel has not enabled SME via any means then * don't advertise the SME feature. * For SEV: If BIOS has not enabled SEV then don't advertise the - * SEV and SEV_ES feature (set in scattered.c). + * SEV, SEV_ES and SEV_SNP feature. * * In all cases, since support for SME and SEV requires long mode, * don't advertise the feature under CONFIG_X86_32. @@ -594,6 +594,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) clear_sev: setup_clear_cpu_cap(X86_FEATURE_SEV); setup_clear_cpu_cap(X86_FEATURE_SEV_ES); + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); } } diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 73e643ae94b6..a636342ecb26 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -405,6 +405,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ /* -- 2.25.1