From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Goldschmidt Date: Fri, 10 Aug 2018 14:56:42 +0200 Subject: [U-Boot] [PATCH] arm: socfpga: make socfpga_socrates_defconfig boot from QSPI In-Reply-To: <8c12ed86-8156-f730-4491-e164c9632ebc@gmail.com> References: <20180806130509.21967-1-simon.k.r.goldschmidt@gmail.com> <1f5e8a25-55c6-ada0-9c01-d42a94980ba8@denx.de> <8c12ed86-8156-f730-4491-e164c9632ebc@gmail.com> Message-ID: <7b1e9dac-62e5-5223-e578-90b3ba5140bd@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09.08.2018 23:57, Marek Vasut wrote: > On 08/09/2018 09:17 PM, Simon Goldschmidt wrote: >> [..] >> BTW, the DIP switches even allow the SoCrates to boot from fpga, which >> is what I'm currently working on. In this case, it seems like we need >> a separate config at least, but the dts can still be the same. > Presumably because the SPL needs different link address ? The linker address of course needs to be changed. Preventing the cpu accessing the FPGA OnChip RAM was a bit more tricky to debug, but it seems I have it working now. I guess we need a Kconfig option to enable the bridge reset changes and select the correct link address. I'll prepare a patch for that. Should I base it on top of my gen5 fixes series? Additionally, to add the binary into an fpga, we need a hex file, maybe these can be automatically generated by mach-socfpga's Makefile when creating the SPL... Simon