From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers
Date: Wed, 23 May 2018 09:36:17 -0300 [thread overview]
Message-ID: <7c7c97ef-f41e-b91e-cca9-e29c5ac14a3b@amsat.org> (raw)
In-Reply-To: <1527034517-7851-17-git-send-email-mjc@sifive.com>
On 05/22/2018 09:15 PM, Michael Clark wrote:
> * Add riscv prefix to raise_exception function
> * Add riscv prefix to CSR read/write functions
> * Add riscv prefix to signal handler function
> * Add riscv prefix to get fflags function
> * Remove redundant declaration of riscv_cpu_init
> and rename cpu_riscv_init to riscv_cpu_init
> * rename riscv_set_mode to riscv_cpu_set_mode
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> linux-user/riscv/signal.c | 4 ++--
> target/riscv/cpu.h | 21 ++++++++++-----------
> target/riscv/cpu_helper.c | 10 +++++-----
> target/riscv/csr.c | 8 ++++----
> target/riscv/fpu_helper.c | 6 +++---
> target/riscv/op_helper.c | 28 ++++++++++++++--------------
> 6 files changed, 38 insertions(+), 39 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index ef599e319a10..f03bc7212b49 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -84,7 +84,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> __put_user(env->fpr[i], &sc->fpr[i]);
> }
>
> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> __put_user(fcsr, &sc->fcsr);
> }
>
> @@ -160,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>
> uint32_t fcsr;
> __get_user(fcsr, &sc->fcsr);
> - csr_write_helper(env, fcsr, CSR_FCSR);
> + riscv_csr_write(env, CSR_FCSR, fcsr);
> }
>
> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1ade90d23bbc..d6bb3136db18 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -257,7 +257,7 @@ char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>
> #define cpu_init(cpu_model) cpu_generic_init(TYPE_RISCV_CPU, cpu_model)
> -#define cpu_signal_handler cpu_riscv_signal_handler
> +#define cpu_signal_handler riscv_cpu_signal_handler
> #define cpu_list riscv_cpu_list
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> @@ -265,16 +265,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> #endif
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> void riscv_translate_init(void);
> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> - uint32_t exception, uintptr_t pc);
> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> + uint32_t exception, uintptr_t pc);
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> @@ -294,13 +293,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
>
> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
> - int csrno)
> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> riscv_csrrw(env, csrno, NULL, val, -1);
> }
>
> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
> {
> target_ulong val = 0;
> riscv_csrrw(env, csrno, &val, 0, 0);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 69592c037042..b4bbf7a9fa0a 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> return old;
> }
>
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> g_assert_not_reached();
> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> g_assert_not_reached();
> }
> env->badaddr = addr;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
>
> /* called by qemu's softmmu to fill the qemu tlb */
> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> if (ret == TRANSLATE_FAIL) {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
> }
>
> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_S);
> + riscv_cpu_set_mode(env, PRV_S);
> } else {
> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> env->pc = env->mtvec;
> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_M);
> + riscv_cpu_set_mode(env, PRV_M);
> }
> /* TODO yield load reservation */
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0f886e04b130..45e33d876034 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -95,7 +95,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = cpu_riscv_get_fflags(env);
> + *val = riscv_cpu_get_fflags(env);
> return 0;
> }
>
> @@ -107,7 +107,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> }
> env->mstatus |= MSTATUS_FS;
> #endif
> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> return 0;
> }
>
> @@ -141,7 +141,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> return 0;
> }
> @@ -155,7 +155,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> return 0;
> }
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index fdb87d8d82cb..1452a153f261 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -23,7 +23,7 @@
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> {
> int soft = get_float_exception_flags(&env->fp_status);
> target_ulong hard = 0;
> @@ -37,7 +37,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> return hard;
> }
>
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
> {
> int soft = 0;
>
> @@ -74,7 +74,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
> softrm = float_round_ties_away;
> break;
> default:
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> set_float_rounding_mode(softrm, &env->fp_status);
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 77c79ba36e0b..b7dc18a41e21 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -25,7 +25,7 @@
> #include "exec/helper-proto.h"
>
> /* Exceptions processing helpers */
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> uint32_t exception, uintptr_t pc)
You forgot to remove an extra space to align arguments.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>
> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
> {
> - do_raise_exception_err(env, exception, 0);
> + riscv_raise_exception(env, exception, 0);
> }
>
> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->sepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TSR)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_SPIE));
> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_M)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->mepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_MPIE));
> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TW)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TVM)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> tlb_flush(cs);
> }
>
next prev parent reply other threads:[~2018-05-23 12:36 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-23 0:14 [Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-05-25 15:07 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-23 22:31 ` Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-05-29 23:32 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-05-25 15:15 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-23 23:55 ` Alistair Francis
2018-05-25 15:19 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-05-23 12:23 ` Philippe Mathieu-Daudé
2018-05-25 15:20 ` Richard Henderson
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-29 23:34 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-23 12:25 ` Philippe Mathieu-Daudé
2018-05-29 23:40 ` Alistair Francis
2018-05-23 0:14 ` [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-05-29 23:38 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-05-23 12:26 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-23 12:33 ` Philippe Mathieu-Daudé
2018-05-24 22:47 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-05-23 12:36 ` Philippe Mathieu-Daudé [this message]
2018-05-29 23:43 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Michael Clark
2018-05-23 12:37 ` Philippe Mathieu-Daudé
2018-05-29 23:47 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config Michael Clark
2018-05-23 12:40 ` Philippe Mathieu-Daudé
2018-05-24 22:43 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext Michael Clark
2018-05-23 12:42 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support Michael Clark
2018-05-25 18:53 ` Richard Henderson
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes Michael Clark
2018-05-25 22:40 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads Michael Clark
2018-05-25 22:38 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints Michael Clark
2018-05-24 22:45 ` Alistair Francis
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines Michael Clark
2018-05-23 6:44 ` Laurent Vivier
2018-05-25 7:17 ` Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI Michael Clark
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree Michael Clark
2018-05-23 12:45 ` Philippe Mathieu-Daudé
2018-05-23 0:15 ` [Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload Michael Clark
2018-05-23 12:49 ` Philippe Mathieu-Daudé
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