From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 19 Mar 2019 09:57:12 +0100 Subject: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing In-Reply-To: References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> <1552379474-12867-11-git-send-email-ley.foon.tan@intel.com> Message-ID: <7c89c972-ada2-185b-5e2d-c8c25848f32a@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 3/19/19 4:14 AM, Ley Foon Tan wrote: > On Tue, Mar 12, 2019 at 7:03 PM Marek Vasut wrote: >> >> On 3/12/19 9:31 AM, Ley Foon Tan wrote: >>> Scrub memory content if ECC is enabled and it is not >>> from warm reset boot. >>> >>> Enable icache and dcache before scrub memory >>> and use "DC ZVA" instruction to clear memory >>> to zeros. This instruction writes a cache line >>> at a time and it can prevent false ECC error >>> trigger if write cache line partially. >>> >>> Signed-off-by: Ley Foon Tan >>> --- >>> .../arm/mach-socfpga/include/mach/sdram_s10.h | 9 +++ >>> drivers/ddr/altera/sdram_s10.c | 76 +++++++++++++++++++ >>> 2 files changed, 85 insertions(+) >>> >>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h >>> index 89e355010d..354f80bfce 100644 >>> --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h >>> +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h >>> @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); >>> #define ECCCTRL1 0x100 >>> #define ECCCTRL2 0x104 >>> #define ERRINTEN 0x110 >>> +#define ERRINTENS 0x114 >>> #define INTMODE 0x11c >>> #define INTSTAT 0x120 >>> #define AUTOWB_CORRADDR 0x138 >>> @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); >>> #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) >>> #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f >>> >>> +#define DDR_HMC_ERRINTEN_INTMASK \ >>> + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ >>> + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) >>> + >>> /* NOC DDR scheduler */ >>> #define DDR_SCH_ID_COREID 0 >>> #define DDR_SCH_ID_REVID 0x4 >>> @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); >>> #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ >>> (((x) >> 0) & 0xFF) >>> >>> +/* Firewall DDR scheduler MPFE */ >>> +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 >>> +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) >>> + >>> #endif /* _SDRAM_S10_H_ */ >>> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c >>> index ae4e5ea2fd..2c691d3bee 100644 >>> --- a/drivers/ddr/altera/sdram_s10.c >>> +++ b/drivers/ddr/altera/sdram_s10.c >>> @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs = >>> >>> #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) >>> >>> +#define PGTABLE_OFF 0x4000 >>> + >>> /* The followring are the supported configurations */ >>> u32 ddr_config[] = { >>> /* DDR_CONFIG(Address order,Bank,Column,Row) */ >>> @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void) >>> SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); >>> } >>> >>> +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) >>> +{ >>> + phys_size_t i; >>> + >>> + if (addr % CONFIG_SYS_CACHELINE_SIZE) { >>> + printf("DDR: address 0x%lx not cacheline size aligned.\n", >>> + (ulong)addr); >> >> Is the cast needed ? > Yes, SPL doesn't support %llx, we need cast to ulong %lx. But that doesn't work for 64bit addresses ? Isn't that limitation of tiny printf implementation instead of SPL ? [...] -- Best regards, Marek Vasut