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[83.57.170.138]) by smtp.gmail.com with ESMTPSA id o29sm30961169wra.5.2020.07.14.04.37.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jul 2020 04:37:49 -0700 (PDT) Subject: Re: [PATCH v5 04/11] hw/arm: Add NPCM730 and NPCM750 SoC models To: Havard Skinnemoen , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= References: <20200709003608.3834629-1-hskinnemoen@google.com> <20200709003608.3834629-5-hskinnemoen@google.com> <3ec30463-03f8-98e9-9a14-01b0bb698c9b@kaod.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <7c978e82-8890-9ba4-096a-92d7cff60b0a@amsat.org> Date: Tue, 14 Jul 2020 13:37:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , QEMU Developers , Markus Armbruster , CS20 KFTing , qemu-arm , Joel Stanley , IS20 Avi Fishman Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" +Markus On 7/14/20 2:44 AM, Havard Skinnemoen wrote: > On Mon, Jul 13, 2020 at 8:02 AM Cédric Le Goater wrote: >> >> On 7/9/20 2:36 AM, Havard Skinnemoen wrote: >>> The Nuvoton NPCM7xx SoC family are used to implement Baseboard >>> Management Controllers in servers. While the family includes four SoCs, >>> this patch implements limited support for two of them: NPCM730 (targeted >>> for Data Center applications) and NPCM750 (targeted for Enterprise >>> applications). >>> >>> This patch includes little more than the bare minimum needed to boot a >>> Linux kernel built with NPCM7xx support in direct-kernel mode: >>> >>> - Two Cortex-A9 CPU cores with built-in periperhals. >>> - Global Configuration Registers. >>> - Clock Management. >>> - 3 Timer Modules with 5 timers each. >>> - 4 serial ports. >>> >>> The chips themselves have a lot more features, some of which will be >>> added to the model at a later stage. >>> >>> Reviewed-by: Tyrone Ting >>> Reviewed-by: Joel Stanley >>> Signed-off-by: Havard Skinnemoen >>> --- ... >>> +static void npcm7xx_realize(DeviceState *dev, Error **errp) >>> +{ >>> + NPCM7xxState *s = NPCM7XX(dev); >>> + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); >>> + int i; >>> + >>> + /* CPUs */ >>> + for (i = 0; i < nc->num_cpus; i++) { >>> + object_property_set_int(OBJECT(&s->cpu[i]), >>> + arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), >>> + "mp-affinity", &error_abort); >>> + object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR, >>> + "reset-cbar", &error_abort); >>> + object_property_set_bool(OBJECT(&s->cpu[i]), true, >>> + "reset-hivecs", &error_abort); >>> + >>> + /* Disable security extensions. */ >>> + object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3", >>> + &error_abort); >>> + >>> + qdev_realize(DEVICE(&s->cpu[i]), NULL, &error_abort); >> >> I would check the error: >> >> if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { >> return; >> } >> >> same for the sysbus_realize() below. > > Hmm, I used to propagate these errors until Philippe told me not to > (or at least that's how I understood it). It was before Markus simplification API were merged, you had to propagate after each call, since this is a non hot-pluggable SoC I suggested to use &error_abort to simplify. > I'll be happy to do it > either way (and the new API makes it really easy to propagate errors), > but I worry that I don't fully understand when to propagate errors and > when not to. Markus explained it on the mailing list recently (as I found the doc not obvious). I can't find the thread. I suppose once the work result after the "Questionable aspects of QEMU Error's design" discussion is merged, the documentation will be clarified. My rule of thumb so far is: - programming error (can't happen) -> &error_abort - everything triggerable by user or management layer (via QMP command) -> &error_fatal, as we can't risk loose the user data, we need to shutdown gracefully. > > It makes sense to me to propagate errors from *_realize() and > error_abort on failure to set simple properties, but I'd like to know > if Philippe is on board with that. > >>> + } >>> + >>> + /* A9MPCORE peripherals */ >>> + object_property_set_int(OBJECT(&s->a9mpcore), nc->num_cpus, "num-cpu", >>> + &error_abort); >>> + object_property_set_int(OBJECT(&s->a9mpcore), NPCM7XX_NUM_IRQ, "num-irq", >>> + &error_abort); >>> + sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); >>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); >>> + >>> + for (i = 0; i < nc->num_cpus; i++) { >>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, >>> + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); >>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, >>> + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); >>> + } ...