From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Make intel_{enable, disable}_sagv() static
Date: Sat, 26 Sep 2020 00:28:40 +0000 [thread overview]
Message-ID: <7ccb8fd1f477adebb329578dbd0fcde61de9a80c.camel@intel.com> (raw)
In-Reply-To: <20200925121749.708-1-ville.syrjala@linux.intel.com>
On Fri, 2020-09-25 at 15:17 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <
> ville.syrjala@linux.intel.com
> >
>
> intel_{enable,disable}_sagv() are no longer needed outside the
> compilation unit. Make them static.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <
> ville.syrjala@linux.intel.com
> >
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_pm.h | 2 --
> 2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 34e0d22d456b..8cd62402d597 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3706,7 +3706,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> * - All planes can enable watermarks for latencies >= SAGV engine block time
> * - We're not using an interlaced display configuration
> */
> -int
> +static int
> intel_enable_sagv(struct drm_i915_private *dev_priv)
> {
> int ret;
> @@ -3740,7 +3740,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -int
> +static int
> intel_disable_sagv(struct drm_i915_private *dev_priv)
> {
> int ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index a2473594c2db..eab83e251dd5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -49,8 +49,6 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
> const struct intel_bw_state *bw_state);
> -int intel_enable_sagv(struct drm_i915_private *dev_priv);
> -int intel_disable_sagv(struct drm_i915_private *dev_priv);
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> void intel_sagv_post_plane_update(struct intel_atomic_state *state);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
>
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prev parent reply other threads:[~2020-09-26 0:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-25 12:17 [Intel-gfx] [PATCH 1/2] drm/i915: Make intel_{enable, disable}_sagv() static Ville Syrjala
2020-09-25 12:17 ` [Intel-gfx] [PATCH 2/2] drm/i915: Don't hide the intel_crtc_atomic_check() call Ville Syrjala
2020-09-26 0:28 ` Souza, Jose
2020-09-25 12:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Make intel_{enable, disable}_sagv() static Patchwork
2020-09-25 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-25 17:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-09-26 0:28 ` Souza, Jose [this message]
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