From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6358AC05027 for ; Thu, 2 Feb 2023 14:06:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 68D2585F35; Thu, 2 Feb 2023 15:06:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=collabora.com header.i=@collabora.com header.b="KQ3Tftta"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1999D85F37; Thu, 2 Feb 2023 15:06:19 +0100 (CET) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6E12785EA2 for ; Thu, 2 Feb 2023 15:06:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=reject dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=eugen.hristev@collabora.com Received: from [192.168.0.125] (unknown [82.76.24.202]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madras.collabora.co.uk (Postfix) with ESMTPSA id 148636600013; Thu, 2 Feb 2023 14:06:14 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1675346774; bh=vzv8eDNKsCreCGRpIBpgtT8Urbs8dhiQZKBF2cRWlDU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KQ3Tftta+jnQuE33elob6t9wBmPIkTGkbgm1qz398BMk1RA8MdfUi5r8i08czLwr0 tkCKbgA06STVHn2LN/gDfLO+Yjgg0iDWU7uxtcR7PSAdIwM4wuAnbBTubBDxxBrOK7 t28YmT1WtMmU7UIvXeO64aFFUT5dmdGPtYk94i8yz3D6HOHi19mW/970hXEc8G8pg2 FgQf0pgJHh8fNswL2ld6tgm4ehCxYEC/RzTcHE74QijUm/DIO5/z5bUyDSFgLB2FWb QLuse6malKCXthktzPzJqj4oKm74rc6hKHf9PZekkX6csxqC9LA1e7M9BgY/27EbaN +K2od2suCM06w== Message-ID: <7d1c66c2-f747-e1d0-b27d-5eecbdbe05b3@collabora.com> Date: Thu, 2 Feb 2023 16:06:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [RFC PATCH 11/16] arm64: dts: rockchip: Add base DT for rk3588 SoC Content-Language: en-US To: Jagan Teki , Kever Yang , Simon Glass , Philipp Tomsich , fatorangecat@189.cn Cc: u-boot@lists.denx.de, Jianqun Xu References: <20230125222741.303259-1-jagan@edgeble.ai> <20230125222741.303259-12-jagan@edgeble.ai> From: Eugen Hristev In-Reply-To: <20230125222741.303259-12-jagan@edgeble.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 1/26/23 00:27, Jagan Teki wrote: > This initial version supports CPU, dma, interrupts, timers, UART and > SDHCI (everything necessary to boot Linux on this system on chip) as > well as Ethernet, I2C, PWM and SPI. > > The DT is split into rk3588 and rk3588s, which is a reduced version > (i.e. with less peripherals) of the former. > > commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588 > SoC") > commit ("arm64: dts: rockchip: Add rk3588 pinctrl data") > > Signed-off-by: Jianqun Xu > Signed-off-by: Kever Yang > Signed-off-by: Jagan Teki [snip] > + > + cru: clock-controller@fd7c0000 { > + compatible = "rockchip,rk3588-cru"; > + reg = <0x0 0xfd7c0000 0x0 0x5c000>; > + assigned-clocks = > + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, > + <&cru PLL_NPLL>, <&cru PLL_GPLL>, > + <&cru ACLK_CENTER_ROOT>, > + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, > + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, > + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, Hi Jagan, This clock PCLK_PMU0_ROOT is assigned here a clock rate (100 Mhz), but your patch clk: rockchip: Add rk3588 clk support , in function rk3588_clk_set_rate , does not take into account the PCLK_PMU0_ROOT , hence there is an error printed : rk3588_clk_set_rate(clk=37fc28, rate=100000000): unknown clock id=646 (switch statement exits on default branch ) Could you have a look please? Thanks, Eugen > + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, > + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, > + <&cru CLK_GPU>; > + assigned-clock-rates = > + <100000000>, <786432000>, > + <850000000>, <1188000000>, > + <702000000>, > + <400000000>, <500000000>, > + <800000000>, <100000000>, > + <400000000>, <100000000>, > + <200000000>, <500000000>, > + <375000000>, <150000000>, > + <200000000>; > + rockchip,grf = <&php_grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > +