From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner
Date: Tue, 10 Oct 2017 10:00:25 +0200 [thread overview]
Message-ID: <7d9413a9-0c4f-bd07-c428-83c0925be9ee@denx.de> (raw)
In-Reply-To: <97aac252-e555-a24a-e236-96fa68540bea@ti.com>
On 10/10/2017 07:48 AM, Kishon Vijay Abraham I wrote:
> Hi,
Hi,
[...]
>>>>>>>>>>> - dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
>>>>>>>>>>> + dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2);
>>>>>>>>>>
>>>>>>>>>> Why *2 ?
>>>>>>>>>
>>>>>>>>> Because its allocated as sizeof(*dwc->ep0_trb) * 2 below. This is not
>>>>>>>>> strictly required as dwc3_flush_cache() rounds up the size to
>>>>>>>>> CACHELINE_SIZE but from a caller POV, flush everything we allocated.
>>>>>>>>
>>>>>>>> Can the other TRB be in use ? Maybe aligning the TRBs to cacheline size
>>>>>>>> would be better ?
>>>>>>>>
>>>>>>> A single trb is 16 bytes in size and two of them are allocated
>>>>>>> contiguously.
>>>>>>
>>>>>> Why are two allocated continuously ? (I am not dwc3 expert)
>
> The TRB's should be allocated contiguously for dwc3 and only the base of the
> entire TRB table is programmed in the HW.
> ________________ <------------------ TRB table base address
> | TRB0 |
> |________________|
> | TRB1 |
> |________________|
> | TRB2 |
> |________________|
> | TRBn |
> |________________|
>
>
>>>>>
>>>>> Neither am I. I did try to pad to the dwc_trb structure such that each
>>>>> trb is 64 bytes in size but this leads to failures when testing. I
>>>>> didn't get a chance to debug this though. I suspect its because the code
>>>>> expects the trbs to be contiguous and/or 16 bytes in size.
>
> It's not the code but it's the HW.
That'd imply we need either some sort of flushing scheme or non-cachable
memory allocation. What does Linux do ?
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2017-10-10 8:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 11:15 [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner Faiz Abbas
2017-10-03 7:35 ` Faiz Abbas
2017-10-03 9:08 ` Andy Shevchenko
2017-10-03 9:43 ` Marek Vasut
2017-10-03 9:58 ` Faiz Abbas
2017-10-03 12:04 ` Marek Vasut
2017-10-03 12:18 ` Dr. Philipp Tomsich
2017-10-03 12:52 ` Marek Vasut
2017-10-03 13:17 ` Faiz Abbas
2017-10-03 13:18 ` Marek Vasut
2017-10-04 10:51 ` Faiz Abbas
2017-10-04 12:31 ` Marek Vasut
2017-10-04 13:11 ` Faiz Abbas
2017-10-05 11:27 ` Marek Vasut
2017-10-06 11:33 ` Faiz Abbas
2017-10-10 5:37 ` Faiz Abbas
2017-10-10 5:48 ` Kishon Vijay Abraham I
2017-10-10 8:00 ` Marek Vasut [this message]
2017-10-10 10:45 ` Faiz Abbas
2017-10-10 13:49 ` Marek Vasut
2017-10-11 8:23 ` Faiz Abbas
2017-10-11 8:58 ` Kishon Vijay Abraham I
2017-10-11 13:23 ` Faiz Abbas
2017-10-03 13:01 ` Marek Vasut
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