From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH 2/9] drm/i915/psr: Don't tell sink that main link will be active while is active PSR2 Date: Wed, 28 Nov 2018 20:13:30 +0000 Message-ID: <7dff511838472ac205bdda40c6a33eaecb8aa6a0.camel@intel.com> References: <20181127003710.18618-1-jose.souza@intel.com> <20181127003710.18618-2-jose.souza@intel.com> <20181128190218.GI5161@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1463026527==" Return-path: In-Reply-To: <20181128190218.GI5161@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: "Vivi, Rodrigo" Cc: "intel-gfx@lists.freedesktop.org" , "Pandiyan, Dhinakaran" , "dri-devel@lists.freedesktop.org" List-Id: dri-devel@lists.freedesktop.org --===============1463026527== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-85ajUGZu8lIFfbMESYq+" --=-85ajUGZu8lIFfbMESYq+ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2018-11-28 at 11:02 -0800, Rodrigo Vivi wrote: > On Mon, Nov 26, 2018 at 04:37:03PM -0800, Jos=C3=A9 Roberto de Souza > wrote: > > For PSR2 there is no register to tell HW to keep main link enabled > > while PSR2 is active, so don't configure sink DPCD with a > > misleading value. > >=20 > > Cc: Dhinakaran Pandiyan > > Cc: Rodrigo Vivi > > Signed-off-by: Jos=C3=A9 Roberto de Souza > > --- > > drivers/gpu/drm/i915/intel_psr.c | 10 ++++++---- > > 1 file changed, 6 insertions(+), 4 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index f5d27a02eb28..888e348cc1b4 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -391,12 +391,14 @@ static void intel_psr_enable_sink(struct > > intel_dp *intel_dp) > > drm_dp_dpcd_writeb(&intel_dp->aux, > > DP_RECEIVER_ALPM_CONFIG, > > DP_ALPM_ENABLE); > > dpcd_val |=3D DP_PSR_ENABLE_PSR2; > > + } else { > > + if (dev_priv->psr.link_standby) > > + dpcd_val |=3D DP_PSR_MAIN_LINK_ACTIVE; > > + > > + if (INTEL_GEN(dev_priv) >=3D 8) > > + dpcd_val |=3D DP_PSR_CRC_VERIFICATION; >=20 > commit message only mention the link stand-by... > could you please do this in a separated patch? We were already doing it for PSR1, I just grouped all the PSR1 checks inside of this else block, so there is no functional change in CRC verification but I can move it to a separated patch if you want. >=20 > > } > > =20 > > - if (dev_priv->psr.link_standby) > > - dpcd_val |=3D DP_PSR_MAIN_LINK_ACTIVE; > > - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >=3D 8) > > - dpcd_val |=3D DP_PSR_CRC_VERIFICATION; > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > =20 > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); > > --=20 > > 2.19.2 > >=20 --=-85ajUGZu8lIFfbMESYq+ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlv+9ugACgkQVenbO/mO WkkFlggAhoVEjtdaFTTo/erMAq+s0yq+qX58fANQu2NifmLt+uZQ6Htp0aHELhkz Ko/Dk+gwZOyVFWUesqa9F6AkC+4Zm0bRTMkOs/9ykFINuF+sXqdCY/Q6lLv3zF2W FqNJI7xTNi5jGeNxXRJHoo6vVIA94p4kGO5KswDlp1oetgDqCGlBb+PkGTOvRp3X SD2nX64Cj61ARmOOOZqX5oci3BDejpGbcsKuTKqcbXa1kQmK+pdbTlYUAw6SM+lV grY+mpqvFxpMlfrYs+8BL3pvmYnfOazqxlUeXhFEdhx8v7QsbjEFjXJvHvcGI89c txT8K+oFH/jfgv9a2OGwmTh7YowwuQ== =VfsU -----END PGP SIGNATURE----- --=-85ajUGZu8lIFfbMESYq+-- --===============1463026527== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============1463026527==--