From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,PDS_BAD_THREAD_QP_64,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71C1CC433B4 for ; Wed, 28 Apr 2021 03:35:06 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id C541D61042 for ; Wed, 28 Apr 2021 03:35:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C541D61042 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE41540147; Wed, 28 Apr 2021 05:35:04 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id B553140041 for ; Wed, 28 Apr 2021 05:35:02 +0200 (CEST) IronPort-SDR: RizaEHSkx2iVRTxXoZIdj6N3sFLxA3uhqqeHIKRitYGPGzBg3nMjz6fR6XpyGH+8flnG3zTrWq 3n0/Prqao0gQ== X-IronPort-AV: E=McAfee;i="6200,9189,9967"; a="193457859" X-IronPort-AV: E=Sophos;i="5.82,257,1613462400"; d="scan'208";a="193457859" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2021 20:35:01 -0700 IronPort-SDR: ak6ayfNsElLK2+MCHg0kBJKQj8pvEbyqshb2xM2R94QeT4OZUKwqDD7X+h52fFuiiENiIxn9Vf Ef2AwI3aayXw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,257,1613462400"; d="scan'208";a="386365088" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2021 20:35:01 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 27 Apr 2021 20:35:00 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Wed, 28 Apr 2021 11:34:58 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2106.013; Wed, 28 Apr 2021 11:34:58 +0800 From: "Zhang, Qi Z" To: "Wang, Haiyue" , "dev@dpdk.org" CC: "Wang, Liang-min" , "david.marchand@redhat.com" , "Wu, Jingjing" , "Xing, Beilei" Thread-Topic: [PATCH v4 2/3] net/iavf: enable PCI bus master after reset Thread-Index: AQHXO25dzEpoce0CO0WNxCrNAxLv6arJR/Rw Date: Wed, 28 Apr 2021 03:34:58 +0000 Message-ID: <7e6bf3d78c4f46b6a3b4a6136555f473@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210427133912.261993-1-haiyue.wang@intel.com> <20210427133912.261993-3-haiyue.wang@intel.com> In-Reply-To: <20210427133912.261993-3-haiyue.wang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Wang, Haiyue > Sent: Tuesday, April 27, 2021 9:39 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z ; Wang, Liang-min > ; david.marchand@redhat.com; Wang, Haiyue > ; Wu, Jingjing ; Xing, Beil= ei > > Subject: [PATCH v4 2/3] net/iavf: enable PCI bus master after reset >=20 > The VF reset can be triggerred by the PF reset event, in this case, the P= CI bus > master will be cleared, then the VF is not allowed to issue any Memory or= I/O > Requests. >=20 > So after the reset event is detected, always enable the PCI bus master. >=20 > Signed-off-by: Haiyue Wang > --- > drivers/net/iavf/iavf_ethdev.c | 3 +++ > 1 file changed, 3 insertions(+) >=20 > diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethde= v.c > index d523a0618..9a0a20a29 100644 > --- a/drivers/net/iavf/iavf_ethdev.c > +++ b/drivers/net/iavf/iavf_ethdev.c > @@ -2255,6 +2255,9 @@ iavf_dev_close(struct rte_eth_dev *dev) > rte_free(vf->aq_resp); > vf->aq_resp =3D NULL; >=20 > + if (vf->vf_reset) > + rte_pci_set_bus_master(pci_dev, true); > + > vf->vf_reset =3D false; >=20 > return ret; > -- > 2.31.1 Acked-by: Qi Zhang